CSC ME1/1 Patch Panel Interconnect Board (PPIB) Mikhail Matveev Rice University February 27, 2013

TTC Signal Distribution to ME1/1 (1) February 27, 2013 CSC ME1/1 Electronics System Review2 ● The original plan was to implement fully optical communication path between the ME1/1 on-chamber electronics and a peripheral crate: - Comparator hits (trigger path) are delivered from DCFEB to TMB via optical links (FPGA – to – FPGA) - Optical data readout from DCFEB to ODMB (FPGA – to – FPGA) - 15 TTC signals are delivered to/from DCFEBs from/to ODMB via duplex optical links using the FF_EMU ASIC and a custom FF_LYNX protocol ● After ~6 months of tests the FF_EMU ASIC has not been proven to work as expected ● Solution: replace optical TTC link to DCFEBs with a copper one - In the present design there are 5 cables from the DMB front panel to CFEBs - There is not enough space to attach 7 cables to the front panel of the new DCFEB - Need to use a patch panel residing on the chamber and chose optimal number of cables and signals to be transmitted from/to the ODMB - Take advantage of using existing skewclear copper cables

TTC Signal Distribution to ME1/1 (2) February 27, 2013 CSC ME1/1 Electronics System Review3 ● We considered 2 PPIB options: - Passive board with 4 cables coming from the ODMB and 7 cables to DCFEB - Active board with 2 cables coming from the ODMB, active circuitry and 7 cables to DCFEBs ● Passive PPIB: - Simpler design - On ODMB: very hard to squeeze 4 copper cables to PPIB, another copper cable to LVMB, optical module and other parts into a single width VME front panel ● Active PPIB: - Need active circuitry on the board (but with simple functionality) - Two HD50 connectors fit the front panel of the ODMB very well. This is our choice.

Connection Diagram February 27, 2013 CSC ME1/1 Electronics System Review4

Patch Panel Interconnect Board (1) February 27, 2013 CSC ME1/1 Electronics System Review5 ODMB cables DCFEB cables ● 2 skewclear cables to ODMB, 7 custom cables to DCFEBs ● 2 PPIB boards in the patch panel box ● Simple circuitry (3 types of LVDS/LVTTL drivers/receivers, all tested and being used on DCFEB) ● Low power from ODMB (<1A estimated)

Patch Panel Interconnect Board (2) February 27, 2013 CSC ME1/1 Electronics System Review6 ● Board dimensions 250 x 160 mm ● Mechanical design is well specified by Dubna group

PPIB Design Status and Plans February 27, 2013 CSC ME1/1 Electronics System Review7 ● Schematic design: finalized at Rice in mid February (driven by the ODMB schematic) ● PCB layout design: started at CERN on February 22 nd. Hope to go to PCB production (15 boards) by March 8. ● Expect to have 4 bare boards at Rice by the end of March and quickly assemble them here ● By that time the ODMB board Ver.2 should also be here at Rice and (at least partially) debugged. Since we have the DCFEB board and two skewclear cables, the whole chain ODMB-PPIB-DCFEB can be tested at Rice ● If successful, assemble the remaining 11 boards at CERN. Launch production of 90 boards in April through CERN. ● The cost of parts for the production PCB is ~$130