Department of Communication Engineering, NCTU 1 Unit 4 Arithmetic and Logic Units

Department of Communication Engineering, NCTU Serial Adder with Accumulator

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 3 We design a control circuit for a serial adder with an accumulator

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 4 Operation

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 5 State graph for serial adder control

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 6

7 4.2 A Parallel Multiplier

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 8 A multiplier for binary positive number Save the product in a register Shift the product to the right each time

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 9 Datapath of the multiplier

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 10 Operation for a simple example

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 11 State graph for a straightforward implementation

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 12 An alternative approach

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 13 Operation using a counter

Department of Communication Engineering, NCTU A binary Divider

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 15 A parallel divider for positive numbers A circuit to divide an 8-bit dividend by a 4-bit divisor to obtain a 5-bit quotient

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 16 Block diagram  Store the dividend in a register  Shift the dividend to the left each time  An extra bit is required on the left end of the dividend register

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 17 The operation for an example  Load initial data  Subtraction cannot be carried out without a negative result  Thus, shift the dividend to the left before we subtract

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 18  The quotient digit of 1 is stored in the unused position of the dividend register  Shift the dividend one place to the left  Shift once again The first quotient digit

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 19  Subtraction is carried out, and the 3rd quotient digit of 1 is stored in the unused position of the dividend register  A final shift is carried out, and the 4th quotient bit is set to zero What if the quotient is too large > 4 bits  If the initial left five bits  the divisor  overflow

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 20 Datapath

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 21 The state graph  If X 8 X 7 X 6 X 5 X 4  Y 3 Y 2 Y 1 Y 0  C =1  Sh and Sub and the quotient bit is 1  Otherwise  Sh and the quotient bit is 0

Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 22 Implementation with the one-hot assignment