EE115C – Spring 2010 Digital Electronic Circuits Presentation Template

Area-Delay Optimization for a 10-bit Carry-Select Adder

3 Design Summary  A) Adder block topology, B) Circuit Style Square root carry select adder  C) WHY: about Area, about Delay, other Faster than a linear carry select adder *Replace [] with your numbers: e.g. t p = 0.65ns etc. EE115C – Spring 2010 SchematicLayout sizeMetricVerify t p_ci→co = 3.34 ns X= 29.8um, Y= 29.8um t p × Area = 3.0e-12Func: N t p_ci→s9 = 2.68 ns Area = 0.9mm 2 DRC: N T p = [] nsLVS: N

4 Critical Path Analysis  Highlight critical path – block diagram of design / crit-path delay equation EE115C – Spring 2010 t-crit = t-setup + t-carry + 2sqrt(5)t-mux + t-sum

5 Design Optimization  gate level critical path  MOS detail of gates & sizing strategy EE115C – Spring 2010 Focused on area  Want to make sure that the full adders and the multiplexers fit into a square area  Used divisible dimensions in order to ensure modular design  Used precision (ie 0.005) placement in order to minimize area spent on satisfying design rules Some attention to delay

6 Functionality Check  Screenshot of relevant waveforms EE115C – Spring 2010

7 Adder Layout EE115C – Spring 2010

8 Discussion  Three most important features of your design – Square route carry select is faster than linear – Used mirror adders because they use less transistors – Organized layout makes working with it systematic  Given another chance, 3 things you would do different – Choose a straightforward design so the layout would be simpler – Spend more attention on delay/sizing up front – Favor consistent design strategies from the beginning EE115C – Spring 2010