STRJ-WG1 April 21, Proposed Roadmap Tables on SOC Low Power STRJ-WG1 June 2001 This is an updated version of SoC Low Power Roadmap from STRJ-WG1 developed in 1999

STRJ-WG1 April 21, SOC Low Power Premises & Prospects Technology Node, ASIC Usable Transistors, DRAM capacity, and Power Supply Voltage conform to ITRS2000 update SC2.0. Application is not specified, but surely it is high-end SOC in each generation. Other premises or prospects are consistent with those of “SOC Design Productivity”, such as ; Die size remains around 10mm Operation frequency goes up from 150MHz(1999) to 2500MHz(2014). Logic gate count ratio continuously decreases. Low Power

STRJ-WG1 April 21, SOC Low Power (cont.) Assumptions Power consumption follows a basic well-known formula, that is Power ∝ C * V * V * f. “C” can be decomposed into “size factor” and “process factor”. Total transistor count and technology node represents “size factor” and “process factor”, respectively. “V*V” is considered as “voltage factor”, and it is just internal voltage. Also, “f” is considered as “frequency factor”, and it is just max frequency. “total power trend” is defined as relative amount of power consumption for each year(2001, 2004, 2011 and 2014) comparing each of above four “factor” for 1999 as unit(=1). Low Power

STRJ-WG1 April 21, SOC Low Power (cont.) Assumptions (cont.) “total power trend” is derived by the following calculation, “total power trend” = “size factor” x “process factor” x ”voltage factor” x “frequency factor” Current SOC power consumption is assumed around 3W. For “size factor”, constant coefficient 0.85 is applied to Memory portion, while 1.0 to Logic portion. Low Power

STRJ-WG1 April 21, SOC Low Power (cont.) How to derive “Total Power trend” and “Power estimation” Total Power trend Power estimation (W) = (Total Power Trend) x 3W (Ex.) in 2004 Total Power trend = 7.71 x 0.50 x 0.36 x 6.67 = 9.25 Hence, Power estimation( W ) = 9.25 x 3 = W = “size factor” x “process factor” x ”voltage factor” x “frequency factor” Low Power

STRJ-WG1 April 21, SOC Low Power (cont.) Low Power

STRJ-WG1 April 21, SOC Low Power Table Low Power

STRJ-WG1 April 21, SOC Low Power Design Low Power - Potential Solution Map -

STRJ-WG1 April 21, Low Power SOC Low Power Design - Potential Solution Map - What this figure means …. Trade-off line between operation frequency and size(Mtr) is put for each Technology node under the condition to accomplish 0.5W power consumption. A set of potential low power technology is overlaid in accordance with those contribution area and degree of range. Each potential technology is classified into three types( speed, size, and all ) with respect to main contribution.

STRJ-WG1 April 21, Low Power SOC Low Power Design Appendix The following two pages are Low Power table and solution map developed by STRJ-WG1 in 1999 based upon ITRS1999 data

STRJ-WG1 April 21, SOC Low Power Table Low Power STRJ-WG Version

STRJ-WG1 April 21, Low Power - Potential Solution Map - STRJ-WG Version