LLRF FOR CHOPPER Grégoire Hagmann Philippe Baudrenghien BE/RF/FB February 24th, 2013

Block Diagram LLRF Linac 4, G.Hagmann 2 Chopping «pattern» Plates delay adjustment Monitoring (Waveform & chopping time) Interlocks

Location “CDU” LLRF Linac 4, G.Hagmann 3 Rack AY01

LLRF Linac 4, G.Hagmann 4 BIS cables arrivals Need of space for transition patch panel : 2U Need 1U Beam permit patch =>TE/MPE/EP Need 1U User permit parch Who? BE/RF or TE/MPE? Position for BIS patch-panels? Transition patch needed No Burndy on VME board

Chopper Limitations Max Chopper pulse length : 500us (programmable) => need monitoring (start counter at “source on”) => Drive off when “source off” => Drive off when >500us (timeout) from “source on” => What if timeout? Alarm? User Permit False? OP action? LLRF Linac 4, G.Hagmann 5 <500us

Ring blanking LLRF Linac 4, G.Hagmann 6 Discussion with A.Blas Compatible with booster? (Magnetic compensation in RF lowlevel…) Reaction time for ring interlock?

Ring blanking LLRF Linac 4, G.Hagmann 7 During the Linac 4 pulse (window), Can one ring be inhibited? And does it need immediate action? If YES : → “Dynamic” Ring blanking → Need timing ring identification → Need 1 chopping pattern table per ring → Need accurate HW timing(s) for re-synchronization If NO : Can 1 ring interlock be interpreted like a change in nb of turn of the ring? If YES: → High level software re-compute chopping pattern (new settings) → Load of the new chopping pattern and played for next cycle/user If NO: → No change in chopping pattern table → Need ppm information for which ring are “played” (Timing or with Software)

L4-Booster synchronization LLRF Linac 4, G.Hagmann 8 Beam must be chopped during the 1us PSB ring change References document : Synchronization between Linac4 and the PS Booster CERN-ATS-Note solutions : Synchronization for every Ring “Dynamic” ring blanking feasible Accurate synchronization signals => accuracy? 1 “pattern” table for every ring Table switching 1 single synchronization after “Source On” timing start No “Dynamic” ring blanking (or more complex => to be studied) 1 accurate synchronization signal 1 “pattern” table for all rings No distinction if 1 or more ring => “just” one chopping pattern RF frequencies (L4 & booster) stability? RF Linac4 HW timing T r << T RF T RF ≈ 2.84ns

L4-Booster synchronization LLRF Linac 4, G.Hagmann 9 3 Proposals : Re-synchronization for every ring (Meeting Dec 16 th 2011) 4 timings CTRV (next Ring identifier) 1 accurate HW timing at every ring start Dynamic ring blanking feasible Safer, consistency between Chopper and PSB injection Distributor 1 timings CTRV (source on) 1 accurate HW timing at the window start (linac 4 pulse) 1 pattern table for 4 rings No Dynamic ring blanking Need new setting (at the next cycle) for new pattern 4 accurate HW timings, 1 per ring (ring start) Dynamic ring blanking feasible HW More complex, More cabling

L4-Booster synchronization LLRF Linac 4, G.Hagmann 10 exemple 4 timings CTRV (next Ring identifier) 1 accurate HW timing at every ring start Dynamic ring blanking feasible Safer, consistency between Chopper and PSB injection Distributor Ring 1 start HW timing Ring 2 start Ring 3 start Ring 4 start

CDU details LLRF Linac 4, G.Hagmann 11

CDU details LLRF Linac 4, G.Hagmann 12 From & To BIS (No fiber anymore) RF Interlock crate Start & Stop independent adjustable delays for all plates

CDU details LLRF Linac 4, G.Hagmann 13 VME board “RF” type BIS input & output on LEMO EPG.0B.304.HLN (or similar) XXX.1B.308.XXX RF Interlock 1 interlock or 2 interlocks (1 per chopper) ? From AY01 Optical, Multi-mode, ST Same for cavity-controller PIMS, CCDTL…) TX pulses monitoring Veto Diagnostics

BIS «gating» LLRF Linac 4, G.Hagmann 14  Gating with timing from BE/CO (CTRV) ?  Fail safe?  Gating rather in the BIS than CDU ? Gating ON BIS event Latched Gating OFF Chopper forced OFF BIS even unlatched

New special «BI» timing Addition of a new «CTRV like» timing feasible Not fail safe 2 solutions: Implemented HW similar to the BIS signal => Fixed implementation => Simple functionality => “Robust” => Timing always needed Through FPGA => Flexible implementation => Complex functionality possible Timing Hardware? LLRF Linac 4, G.Hagmann 15

New special «BI» timing LLRF Linac 4, G.Hagmann 16 Chopper ON Chopper OFF Chopper ON (latched)

RF Interlock LLRF Linac 4, G.Hagmann 17 « Phoenix contact » module open (example of a design) « Phoenix contact » module closed Power side (PLC) : LowLevel side : ST optical receiver on CDU board By-pass input foreseen for “debug & tests”

LLRF Linac 4, G.Hagmann 18