University of Rostock Institute of Applied Microelectronics and Computer Engineering Monitoring and Control of Temperature in Networks-on- Chip Tim Wegner,

Slides:



Advertisements
Similar presentations
Heat Generation in Electronics Thermal Management of Electronics Reference: San José State University Mechanical Engineering Department.
Advertisements

Practical Aspects of Reliability Analysis for IC Designs T. Pompl, C. Schl ü nder, M. Hommel, H. Nielen, J. Schneider.
Reliability Enhancement via Sleep Transistors Frank Sill Torres +, Claas Cornelius*, Dirk Timmermann* + Department of Electronic Engineering, Federal University.
Algorithm for Fast Statistical Timing Analysis Jakob Salzmann, Frank Sill, Dirk Timmermann SOC 2007, Nov ‘07, Tampere, Finland Institute of Applied Microelectronics.
TO COMPUTERS WITH BASIC CONCEPTS Lecturer: Mohamed-Nur Hussein Abdullahi Hame WEEK 1 M. Sc in CSE (Daffodil International University)
Introduction to CMOS VLSI Design Lecture 21: Scaling and Economics
Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide Breakdown Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn,
Zhang Fu, Marina Papatriantafilou, Philippas Tsigas Chalmers University of Technology, Sweden 1 ACM SAC 2010 ACM SAC 2011.
Reporter: Bo-Yi Shiu Date: 2011/05/27 Virtual Point-to-Point Connections for NoCs Mehdi Modarressi, Arash Tavakkol, and Hamid Sarbazi- Azad IEEE TRANSACTIONS.
On Modeling the Lifetime Reliability of Homogeneous Manycore Systems Lin Huang and Qiang Xu CUhk REliable computing laboratory (CURE) The Chinese University.
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.
Low Power Design for Wireless Sensor Networks Aki Happonen.
MICRO-MODEM RELIABILITY SOLUTION FOR NOC COMMUNICATIONS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar Technion – Israel.
MINIMISING DYNAMIC POWER CONSUMPTION IN ON-CHIP NETWORKS Robert Mullins Computer Architecture Group Computer Laboratory University of Cambridge, UK.
Design and Implementation of VLSI Systems (EN0160)
מודלים של חיבורי ביניים מודלים חשמליים של חיבורי ביניים עבור מעגלי VLSI פרופ ’ יוסי שחם המחלקה לאלקטרוניקה פיזיקלית, אוניברסיטת ת ” א.
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 18: Scaling Theory Prof. Sherief Reda Division of Engineering, Brown University.
From Compaq, ASP- DAC00. Power Consumption Power consumption is on the rise due to: - Higher integration levels (more devices & wires) - Rising clock.
1 Temperature-Aware Resource Allocation and Binding in High Level Synthesis Authors: Rajarshi Mukherjee, Seda Ogrenci Memik, and Gokhan Memik Presented.
1 Evgeny Bolotin – ClubNet Nov 2003 Network on Chip (NoC) Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny ClubNet - November.
1 Evgeny Bolotin – ICECS 2004 Automatic Hardware-Efficient SoC Integration by QoS Network on Chip Electrical Engineering Department, Technion, Haifa, Israel.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.
Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation Andrew B. Kahng †, Sung-Mo Kang ‡, Wei Li ‡, Bao Liu † † UC.
Introduction to CMOS VLSI Design Lecture 21: Scaling and Economics Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.
University of Michigan Electrical Engineering and Computer Science 1 Online Timing Analysis for Wearout Detection Jason Blome, Shuguang Feng, Shantanu.
Network-on-Chip: Communication Synthesis Department of Computer Science Texas A&M University.
Understanding Network Failures in Data Centers: Measurement, Analysis and Implications Phillipa Gill University of Toronto Navendu Jain & Nachiappan Nagappan.
Items for Discussion Chip reliability & testing Testing: who/where/what ??? GBTx radiation testing GBTx SEU testing Packaging – Low X0 options, lead free.
Design, Synthesis and Test of Network on Chips
G.K.BHARAD INSTITUTE OF ENGINEERING DIVISION :D (C.E.) Roll Number :67 SUBJECT :PHYSICS SUBJECT CODE : Presentation By: Kartavya Parmar.
Clockless Chips Date: October 26, Presented by:
Lecture 03: Fundamentals of Computer Design - Trends and Performance Kai Bu
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Color.
Total Dose Effects on Devices and Circuits - Principles and Limits of Ground Evaluation-
Moisture impact on building rocks - the laboratory and in situ investigations FIDRÍKOVÁ D., KUBIČÁR Ľ. Institute of Physics SAS, Bratislava, Slovakia The.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
ECE Advanced Digital Systems Design Lecture 12 – Timing Analysis Capt Michael Tanner Room 2F46A HQ U.S. Air Force Academy I n t e g r i.
Limitations of Digital Computation William Trapanese Richard Wong.
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.
EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Process Variation Mohammad Sharifkhani. Reading Textbook, Chapter 6 A paper in the reference.
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock WIRE WIDENING.
CS 8501 Networks-on-Chip (NoCs) Lukasz Szafaryn 15 FEB 10.
5 장 Dielectrics and Insulators. Preface ‘ Ceramic dielectrics and insulators ’ is a wide-ranging and complex topic embracing many types of ceramic, physical.
11/22/2004EE 42 fall 2004 lecture 351 Lecture #35: data transfer Last lecture: –Communications synchronous / asynchronous –Buses This lecture –Transmission.
Networks-on-Chip (NoC) Suleyman TOSUN Computer Engineering Deptartment Hacettepe University, Turkey.
VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA
ADVANCED HIGH DENSITY INTERCONNECT MATERIALS AND TECHNIQUES DIVYA CHALLA.
1 Presenter: Min Yu,Lo 2015/12/21 Kumar, S.; Jantsch, A.; Soininen, J.-P.; Forsell, M.; Millberg, M.; Oberg, J.; Tiensyrja, K.; Hemani, A. VLSI, 2002.
By Nasir Mahmood.  The NoC solution brings a networking method to on-chip communication.
Computer Science and Engineering Power-Performance Considerations of Parallel Computing on Chip Multiprocessors Jian Li and Jose F. Martinez ACM Transactions.
A Low-Area Interconnect Architecture for Chip Multiprocessors Zhiyi Yu and Bevan Baas VLSI Computation Lab ECE Department, UC Davis.
CS203 – Advanced Computer Architecture
Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
14 February, 2004SLIP, 2004 Self-Consistent Power/Performance/Reliability Analysis for Copper Interconnects Bipin Rajendran, Pawan Kapur, Krishna C. Saraswat.
CARBON NANOTUBES (A SOLUTION FOR IC INTERCONNECT) By G. Abhilash 10H61D5720.
CS203 – Advanced Computer Architecture
The Interconnect Delay Bottleneck.
VLSI design Short channel Effects in Deep Submicron CMOS
Circuits and Interconnects In Aggressively Scaled CMOS
Mission Profile Aware IC Design - A Case Study -
Israel Cidon, Ran Ginosar and Avinoam Kolodny
Challenges in Nanoelectronics: Process Variability
Atomistic simulations of contact physics Alejandro Strachan Materials Engineering PRISM, Fall 2007.
Atomistic materials simulations at The DoE NNSA/PSAAP PRISM Center
Introduction to CMOS VLSI Design Chapter 3: CMOS Processing Technology
Encountering Gate Oxide Breakdown with Shadow Transistors to Increase Reliability Claas Cornelius1, Frank Sill2, Hagen Sämrow1, Jakob Salzmann1, Dirk Timmermann1,
HotAging — Impact of Power Dissipation on Hardware Degradation
Presentation transcript:

University of Rostock Institute of Applied Microelectronics and Computer Engineering Monitoring and Control of Temperature in Networks-on- Chip Tim Wegner, Claas Cornelius, Andreas Tockhorn, Dirk Timmermann; MEMICS 2010, Mikulov, Czech Republic, October 22-24

2 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs Outline 1. Introduction 2. Networks-on-Chip (NoCs) 3. Impact of Temperature on Reliability 4. Monitoring & Control of Temperature in NoCs 5. Summary

3 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 1. Introduction  Increasing integration density → rising complexity, shrinking device sizes  NoCs able to deal with arising requirements (e.g. for communication)  But: Reliability becomes a dominant factor for chip design  Goal: Increase reliability in NoC-based systems  Increasing integration density → rising complexity, shrinking device sizes  NoCs able to deal with arising requirements (e.g. for communication)  But: Reliability becomes a dominant factor for chip design  Goal: Increase reliability in NoC-based systems Impacts of technological development

4 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs Outline 1. Introduction 2. Networks-on-Chip (NoCs) 3. Impact of Temperature on Reliability 4. Monitoring & Control of Temperature in NoCs 5. Summary

5 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 2. Networks-on-Chip  Infrastructure for on-chip interconnection  Point-to-point links replace long global busses  Parallel packet-based communication  Separation of communication & computation  Globally asynchronous locally synchronous (GALS)  Modularity of IP cores (not part of actual NoC)  reusability, high abstraction level  Infrastructure for on-chip interconnection  Point-to-point links replace long global busses  Parallel packet-based communication  Separation of communication & computation  Globally asynchronous locally synchronous (GALS)  Modularity of IP cores (not part of actual NoC)  reusability, high abstraction level Properties NoCs are able to satisfy requirements of modern VLSI systems

6 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs Outline 1. Introduction 2. Networks-on-Chip (NoCs) 3. Impact of Temperature on Reliability 4. Monitoring & Control of Temperature in NoCs 5. Summary

7 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 3. Impact of Temperature on Reliability  Increasing integration densities, progress of nanotechnology  Growing number of transistors per chip = raised probability of failure  decreasing structural size of ICs = higher susceptibility to environmental influences & deterioration  Increasing integration densities, progress of nanotechnology  Growing number of transistors per chip = raised probability of failure  decreasing structural size of ICs = higher susceptibility to environmental influences & deterioration Impacts of technological progress Intel 8086 (1978): ≈879 transistors/mm² Intel Bloomfield (2008): ≈2,78 Mio. transistors/mm²

8 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 3. Impact of Temperature on Reliability  Particular physical effects (e.g. TDDB, EM) contribute to deterioration  Abetted by high temperatures  Correlation between temperature & failure mechanisms established by Arrhenius model  Exponential decrease of IC lifetime with temperature  Particular physical effects (e.g. TDDB, EM) contribute to deterioration  Abetted by high temperatures  Correlation between temperature & failure mechanisms established by Arrhenius model  Exponential decrease of IC lifetime with temperature Why is thermal awareness important? Growing influence of on-chip temperature distribution on lifetime, operability, performance etc.

9 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs Outline 1. Introduction 2. Networks-on-Chip (NoCs) 3. Impact of Temperature on Reliability 4. Monitoring & Control of Temperature in NoCs 5. Summary

 Mitigate effects contributing to deterioration & delay occurrence of failures  Control of on-chip temperature distribution  Mitigate effects contributing to deterioration & delay occurrence of failures  Control of on-chip temperature distribution 10 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4. Monitoring and Control of Temperature for NoCs Objective:  Effective mechanisms to monitor & control on-chip temperature  Integration into existing NoC  Preservation of modularity & reusability  Minimum costs (area, frequency)  Maximum performance of monitoring and control  Minimum impact on system performance  Effective mechanisms to monitor & control on-chip temperature  Integration into existing NoC  Preservation of modularity & reusability  Minimum costs (area, frequency)  Maximum performance of monitoring and control  Minimum impact on system performance Requirements:

11 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4.1 Mechanisms for monitoring Concept: attach physical monitoring probes to every IP core  temperature variation ∆T  Continuous checking of T IPC  |T IPC,old - T IPC,new | ≥ ∆T ?  Report T IPC,new  Area: 66 LUT/FF pairs  Frequency: 227 MHz  temperature variation ∆T  Continuous checking of T IPC  |T IPC,old - T IPC,new | ≥ ∆T ?  Report T IPC,new  Area: 66 LUT/FF pairs  Frequency: 227 MHz Event-driven:  Period of time ∆t  Report T IPC,new every ∆t  Area: 80 LUT/FF pairs  Frequency: 338 MHz  Period of time ∆t  Report T IPC,new every ∆t  Area: 80 LUT/FF pairs  Frequency: 338 MHz Time-driven:

12 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4.2 Mechanisms for control  Reception & interpretation of probe packets  Instructions for Dynamic Frequency Scaling to probes (if necessary)  Area: 507 LUT/FF pairs  Frequency: 165 MHz  Reception & interpretation of probe packets  Instructions for Dynamic Frequency Scaling to probes (if necessary)  Area: 507 LUT/FF pairs  Frequency: 165 MHz Central Control Unit (CCU): !!! Not the smartest approach, but suffices to test functionality !!!

 Area penalty: 30,5%  Freq. penalty: 8,2%  Area penalty: 30,5%  Freq. penalty: 8,2%  Area penalty: 7,3%  Freq. penalty: / (but Mux/Demux)  Area penalty: 7,3%  Freq. penalty: / (but Mux/Demux)  Area penalty: /  Freq. penalty: /  Area penalty: /  Freq. penalty: / 13 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4.3 Integration of monitoring 3 approaches  Different impact on performance & costs Into IP core:Router port of IP core:Extra router port:

14 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4.4 Impact on system performance

15 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 4.5 Performance of monitoring & control

16 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs 5. Summary  Event-driven approach preferable (situational monitoring, better performance, no redundant traffic, lower area costs)  Integration into NoC using router port of IP core best trade-off between costs & preservation of modularity/non-intrusiveness  Event-driven approach preferable (situational monitoring, better performance, no redundant traffic, lower area costs)  Integration into NoC using router port of IP core best trade-off between costs & preservation of modularity/non-intrusiveness Conclusion Implementation of 2 approaches for monitoring on-chip temperature + 3 methods for integration into NoC  Investigation of: Costs (area, frequency) Impact on system performance Performance of monitoring & control

Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Thanks for your attention! Any questions? University of Rostock, Germany Institute of Applied Microelectronics and Computer Engineering Contact: Homepage:

Establishes relationship between temperature and failure mechanisms Describes dependence of chemical reactions on temperature changes Assumption: all other parameters constant 18 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Arrhenius Model Lifetime of ICs decreases exponentially with temperature Monitoring and Control of Temperature in NoCs

19 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Monitoring and Control of Temperature in NoCs  Inoperability of transistor through gate oxide breakdown (long-term) Time Dependent Dielectric Breakdown (TDDB) Formation of charge traps Current flow !!! HEAT !!! More charge traps Conducting path through gate oxide

20 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Transport of material in conductors (i.e. wires) Cause: ion movement induced by current flow (ions’ mobility increases with temperature) Effects: Hillocks  short circuits Voids  interruption of current paths Electromigration (EM) Monitoring and Control of Temperature in NoCs

21 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Intel Bloomfield: Year: Mio. Transistors 263mm² Tr./mm2 Intel 8086: Year: k transistors 33mm² 879 Tr./mm² Intel Processors Monitoring and Control of Temperature in NoCs

22 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Impact on system performance Monitoring and Control of Temperature in NoCs

23 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Performance of monitoring & control Monitoring and Control of Temperature in NoCs

24 Tim Wegner - 23 October 2010 MEMICS 2010, Mikulov, Czech Republic, October Synthesis results for monitoring & control ComponentIntegration method Event- driven probe Time- driven probe Central Control Unit Into IP core Using IP core port Extra port Frequency [MHz] Area [LUT/FF pairs] Unmodified NoC router: 1771 LUT/FF pairs, 122 MHz Monitoring and Control of Temperature in NoCs