Performed By: Yahel Ben-Avraham and Yaron Rimmer Instructor: Mony Orbach Semesterial (possibly bi-semesterial) Winter /12/2012

Introduction  BSV (Bluespec SystemVerilog) High level language Fully synthesizable High simulation capabilities  RISC processor (Reduced Instruction Set Computer) Simple capabilities: pipeline, cache, branch prediction…

Project goals  Goal: Implementing and analyzing RISC Processor using Bluespec  Sub-goals: Learning the working environment and Implementing simple BSV designs Setup and simulate a (modified) RISC processor in BSV environment Synthesize the processor onto FPGA and run tests using SignalTap Performance analysis

Work flow Studying the environment Setting up the RISC processor (virtually) Running simulations and familiarizing Synthesis and analyzing (SignalTap) Performance analysis

Working environment BSV working station ML605 \ ML505 PC

Studying the environment  Setting up the environment  Learning the working environment and Implementing simple BSV designs Architecting and Implementing Microprocessors in Bluespec (summer 2012 course) Lectures and lab exercises. BSV by example (pdf)

Setting up the RISC processor (virtually)  Studying the RISC processor’s general design  Modifying the processor design files

Running simulations and familiarizing with the processor  In-Depth studying of the RISC processor design  Running simulations Running testbenches See the processor in action

Synthesis and analyzing (SignalTap)  Synthesizing the virtual design and downloading to board  Will be using ML605 or ML505  Running testbenches on the downloaded design  Using SignalTap to analyze the performance of the processor

Performance analysis  Assess the processor’s capabilities: Instructions Per Cycle Throughput Latency And perhaps more  Target capabilities will be decided in mid-project presentation.

Timeline Environment setupBSV study and experimentingBegin studying and modifying processor BSV filesBegin virtual setup of the processorMiddle of semester presentation (24-26/12)

General Timeline - project Dec Environment setup, BSV study and experimenting Middle of semester presentation (24-26/12) Jan Studying and modifying processor BSV files Virtual setup of the processor, simulations Feb Tests Low work load Mar Synthesis, on board testbenches and analysis Tests Apr Final presentation

Or else…