Memory-Efficient and Scalable Virtual Routers Using FPGA Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. Authors:Hoang Le, Thilan Ganegedara and Viktor K. Prasanna. Publisher: th ACM/SIGDA international symposium on Field programmable gate arrays (FPGA) Presenter:Chun-Yu, Li Date:2015/11/4

Outline Introduction Network Virtulization IP Lookup Algorithm for Virtual Router Set-Bounded Leaf-Pushing Algorithm (SBLP) Architecture Overall Architecture Memory Management Virtual Routing Table Update Performance Evaluation Experimental Setup Performance Comparison Computer & Internet Architecture Lab CSIE NCKU 2

Network Virtulization (1/2) The main goal of virtualization is to make efficient use of the networking resources. It allows multiple virtual router instances to run on a common physical router platform. Computer & Internet Architecture Lab CSIE NCKU 3

Network Virtulization (2/2) A simple merging algorithm for IP lookup in virtual router that achieves high throughput and supports quick update. Using FPGA along with external SRAM, the proposed architecture can support up to 16M IPv4 and 880K IPv6 prefixes. Computer & Internet Architecture Lab CSIE NCKU 4

Outline Introduction Network Virtulization IP Lookup Algorithm for Virtual Router Set-Bounded Leaf-Pushing Algorithm (SBLP) Architecture Overall Architecture Memory Management Virtual Routing Table Update Performance Evaluation Experimental Setup Performance Comparison Computer & Internet Architecture Lab CSIE NCKU 5

SBLP (1/8) Computer & Internet Architecture Lab CSIE NCKU 6

SBLP (2/8) 1. Move the leaves of the trie into Set 1 Computer & Internet Architecture Lab CSIE NCKU 7

SBLP (3/8) 2. Trim the leaf-removed trie Computer & Internet Architecture Lab CSIE NCKU 8

SBLP (4/8) 3. Leaf-push the resulting trie and move the leaf-pushed leaves into Set 2 Computer & Internet Architecture Lab CSIE NCKU 9

SBLP (5/8) Computer & Internet Architecture Lab CSIE NCKU 10

SBLP (6/8) Computer & Internet Architecture Lab CSIE NCKU 11 All the prefixes in each set are padded with 0 to form the virtual padded prefixes, which are shown in Table 3.

SBLP (7/8) Computer & Internet Architecture Lab CSIE NCKU 12 We propose a memory efficient data structure based on a 2-3 tree, which is a type of B-tree with order of 3. Unlike AVL and Red-Black trees, there is no tree rotation involved when updating a 2-3 tree.

SBLP (8/8) Computer & Internet Architecture Lab CSIE NCKU 13 {VID = 1, IP = }

Outline Introduction Network Virtulization IP Lookup Algorithm for Virtual Router Set-Bounded Leaf-Pushing Algorithm (SBLP) Architecture Overall Architecture Memory Management Virtual Routing Table Update Performance Evaluation Experimental Setup Performance Comparison Computer & Internet Architecture Lab CSIE NCKU 14

Overall Architecture (1/2) Computer & Internet Architecture Lab CSIE NCKU 15 There are 2 pipelines (one for each set of prefixes).

Overall Architecture (2/2) Computer & Internet Architecture Lab CSIE NCKU 16

Memory Management (1/1) Computer & Internet Architecture Lab CSIE NCKU 17 The major difficulty in efficiently realizing a 2-3 tree on hardware. Two memory banks are used to support the node- splitting scheme.

Virtual Routing Table Update (1/3) Computer & Internet Architecture Lab CSIE NCKU 18 A virtual routing table update can be any of three operations: Modification of an existing prefix (i.e. change of the next hop information). Deletion of an existing prefix. Insertion of a new prefix.

Virtual Routing Table Update (2/3) Computer & Internet Architecture Lab CSIE NCKU 19 Find the parent p of the newly inserted node n. There are 2 cases: 1.p has only 2 children

Virtual Routing Table Update (2/3) Computer & Internet Architecture Lab CSIE NCKU 20 2.p has 3 children.

Virtual Routing Table Update (3/3) Computer & Internet Architecture Lab CSIE NCKU 21 1.The memory address to be updated in the next stage 2.The new content for that memory location 3.A write enable bit

Outline Introduction Network Virtulization IP Lookup Algorithm for Virtual Router Set-Bounded Leaf-Pushing Algorithm (SBLP) Architecture Overall Architecture Memory Management Virtual Routing Table Update Performance Evaluation Experimental Setup Performance Comparison Computer & Internet Architecture Lab CSIE NCKU 22

Experimental Setup (1/1) Computer & Internet Architecture Lab CSIE NCKU 23 Group 1 (core IPv4 routing tables) Fourteen experimental IPv4 core routing tables were collected from Project - RIS on 06/03/2010. Group 2 (edge IPv4 routing tables) Synthetic IPv4 routing tables generated using FRuG.(Flexible Rule Generator) Group 3 (edge IPv6 routing tables) The IPv4-to-IPv6 prefix mapping is one-to-one.

Performance Comparison (1/2) Computer & Internet Architecture Lab CSIE NCKU 24 Scheme A1 (Trie-overlapping '08) It is occasionally required to reconstruct the entire lookup data structure for optimal lookup efficiency. Scheme A2 (Trie braiding '10) It is also required to be recomputed over a longer period of time in order to minimize the trie size. Proposed Approach New prefix can quickly be merged using our simple merging algorithm New prefix can be inserted into the tree by injecting the update bubbles into the traffic stream.

Performance Comparison (2/2) Computer & Internet Architecture Lab CSIE NCKU 25 We cannot directly compare the throughput with the other 2 schemes as they were not implemented on hardware. Implementation on FPGA with Virtex-6 XC6VSX475T as the target. 10% of the on-chip logic resource. Throughput of 128 Gbps. Maximum frequency of 200 MHz.