NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Data Compression Module ( DCM ) Tong-Long Fu Laboratory of RF-MW Photonics, Department of Physics National Cheng Kung University, Tainan, Taiwan IFR Status Report

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Review Basic architecture set at PDR meeting At IFR,Status of DCM Design Prototype model Testing DCM Characteristics Will be presented …

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Outline 1. Hardware /Software System Design and specification (1). Prototype Module. (2). Schematic Diagram. (3). FPGA Design (4). Specification and Testing Design Plan (5). Software Code Test (6). CDI Testing 2. DCM working and timing definition 3. DCM Hardware Limitation and Improvement 4. Conclusions and Future Works

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Prototype Module (1) Layer Structure : - Top Level, - Middle Level, - Bottom Level DCM Prototype Testing Board DCM Prototype Testing Board : - includes “DSP Main Board”,”Memory Board”,and “Logic Board” Purpose Purpose : 1. Easy to Test each part of board. 2. Easy to modify any part of board. 3. Easy to develop hardware system

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Prototype Module (2) DSP Main Board : Use ADSP (133 MHz) to test and support stable clock, stable power and JTAG testing port. Memory Board : Use six IDT71024 SRAM and AT28C10 EEPROM to testing

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Prototype Module (3) -Use ICE to test and load test code to DSP ICE can help us to debug DSP and load code. -DSP connect Memory board FPGA also connect after memory board.

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Prototype Module (4) IC Replacement RadiationCustom ChipDifferent Characteristics DSP RH ADSP Custom : Hz The DSP is 4x FPGA RH1280A1280 (A54SX)The first step,we use A54SX to test some ideal. The reason is very simple,because A1280A is to expansive SRAM HX6228IDT71024Power consumption is not the same PROM 27C EEPROM ?Maybe use * AT28C10 During the time of testing, we also use EEPROM to test our code. TTL 74AC1474LS “?” should be provide UCB

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Prototype Module (5) Tools and Devices DeviceCustomPacketQ DSP ADSP DIP * * 2 DSP Lockheed Martin 209A QFP2 FPGA A1280AQFP5 FPGA A54SXVQFP5 SRAM IDT71024SOJ * * 16 EEPROM AT28C10DIP2 TTL 74LS14 (244)DIP>10 OSC 33MHz OscDIP(4pin)>10 Development Tools (hardware) Q ICE-ADSP * * 1 EZ-Lab ADSP DAQ DIO Card 1 DAQ MIO Card 1 FPGA Debug Tool 1 Development Tools (Software) Q ADSP Simulation Tools 1 ADSP Emulation Tools 1 FPGA Desktop Pro 1 FPGA Silicon Explore 1 ADSP C / Assembler Complier 1 * Need to order more for backup

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, FPGA working Flow

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, FPGA Basic Block_Schematic Diagram

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, FPGA Performance and limitation ParameterNumber Gate~ 150 FIFO~ 50 Chip System Gates Logic Gates FIFO I/O (Max) Speed (Max) RT1280A24,00016,000~ MHz A1280A~24,000~16, MHZ A54SX24,00016, MHz - DCM System speed ~ 25MHz Now Used logic Some part we have not add it.include debug part ….

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Circuit Schematic Diagram(1) DSP_Board

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Circuit Schematic Diagram(2) Memory_Board

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Circuit Schematic Diagram(3) Memory_Board

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Simulation environment Testing of Interface : Simulate DPU Action - DAQMIO-16B Card Simulate CDI Information - DAQDIO32HS Card Code Testing -JTAG Testing Port

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM - Software BIOS Code Program Code DCM-Software Code include : Some ideals we had discuss in the SDR and PDR. We need some typical sample picture of “aurora” and “airglow” to do more simulation. Sample Pictures 634X470 (256 Grays) 293KB Org Size: 293KB

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Range Code

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Code Efficiency Coding scheme Sample 1 Sample 2 Sample 3 Sample 4 Huffman codeC. R. = 2.54 Bit Rate = 3.15 C. R. = 2.1 Bit Rate = 3.75 C. R. = 2.17 Bit Rate = 3.7 C. R. = 2.17 Bit Rate = 2.68 Adaptive Huffman code C. R. = 3 Bit Rate = 2.6 C. R. = 2.2 Bit Rate = 3.6 C. R. = 2.25 Bit Rate = 3.56 C. R. = 2.25 Bit Rate = 3.55 Arithmetic code C. R. = 2.55 Bit Rate = 3.13 C. R. = 2.16 Bit Rate = 3.7 C. R. = 2.1 Bit Rate = 3.64 C. R. = 2.2 Bit Rate = 2.63 LZ 77 codeC. R. = 3.54 Bit Rate = 2.26 C. R. = 3 Bit Rate = 2.65 C. R. = 3 Bit Rate = 2.64 C. R. = 3 Bit Rate = 2.64 C. R. : Compression Rate

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Coding scheme Compression code size Decompression code size Huffman code197 KB169KB Adaptive Huffman code 201 KB169 KB Arithmetic code197 KB169 KB Range Code24KB165 KB LZ 77 code193 KB Code Size

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, BIOS Code Size Parameter Parameter Size (bytes) Notes Initial- Routine (BIR)~5Kdefine some parameter Self-Test Routine (BSTR)~5KCheck DCM system is OK CDI Process Routine (BCR)~15K Data transmission Routine(BDTR)~5KControl read and write action Data table: Data initialization Command Table ~15KHaving about data (byte) to use. reserve~10KReserve Block

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, BIOS Work Flow

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Program Section Protocol

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, CDI Simulation (1) Using DIO32HS to simulate CDI Signal -Using external clock to get stable 2 MHz CDI_CLK Command Cycle Timing Readback Cycle Timing

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, CDI Simulation (2) Using LabView to control DIO card, and simulating CDI signal for DCM. For testing environment of DCM,we need create a DTE (DCM testing environment )

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, CDI Stimulation (3) DAQ has internal clock ~20 MHz, but it is not stable when using 2 MHz clock. Use external clock to get a stable signal.

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM _ Work Flow (Defined at SDR,PDR)

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM Interface Signal Timing (1) - Control Line parametertimeunit Trst~100us parametertimeunit Tswb* > 0.4μsμs Tbt> 0.4μsμs Tswb* > 0.4μsμs

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM Interface Signal Timing (2) - Memory Bus for Write Memory parameterMin -- Typical -- Maxunit Tw~ ns Twr~400ns Tawh~ ns Tha ns Thde ns Tde~ ns Tddh~ ns Define at PDR : Access Time = ~ 200 ns

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM Interface Signal Timing (3) - Memory Bus for Read Memory parameter Min --- Typical Maxunit Trw~ ns Trr~ ns Trdh~ ns Trha ns Trhde ~ 180ns

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM Interface Signal Timing - CDI Reference from UCB - Reference from UCB

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Memory Size limitation DCM Module Memory : For DCM Memory Size now is follow limitation further ADSP. If size expansion is necessary,we could modify FPGA code DeviceSize(Now) Max Size Notes BIOS 27C25664k (bytes) 128K (byte) Testing code,initial value Interface Memory of DCM IPM(Internal Program Memory) HX Ea 1024k (words) 1024k (words) Program temp Memory Interface Memory of DCM IDM(Internal Data Memory) HX Ea 1024k (bytes) 1024k (words) Data temp Memory MMCB ??~ support 24 bits address line Up to 32 bits address line Program ; data “?? ” need to specify by UCB

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM Interface : Electric Characteristics for Design Reference ParameterIdeal ConditionsMin MaxUnit Support Volt. ( Vsup ) x V Support Current (Isup) x ? ? mA I/O input Current ( Iin) Vin = Vsup or GND μAμA I/O input Volt. (Vin) x TTL levelV I/O output Current (Iout) Vout = Vsup or GND μAμA I/O output Volt. (Vout) x TTL levelV Control line Volt (Vco) x TTL levelV Control line Current (Ico) Vout = Vsup or GND mA CDI Interface Volt x TTL levelV I/O capacitor x pF -In the finial prototype testing, we will determent all the real testing condition. we estimate its parameter to help us testing. So It is just reference for our design. “?” need to settle by UCB and NCKU together

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, DCM System Specification Parameter Parameter Max Typical Min Max Typical Min unit unit Power Consumption W System speed MHz Data resolution Bits Compression Rate Compression speed (1/frame) * ? μsμs Cost * ?US $ Size5 x 7In^2 Weight~450g “*?” Could you provide us some suggestions?

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Connection Socket - Testing Socket : - Connection to MM : - Connection to DPU : Reference from UCB Maybe use 40 pins connector

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Direction of Improvement item item basic concern / goals Compression Code DesignImprove the size and compression rate of compression code DeviceGet the minimum power consumption All Timing TestingSome timings and compression times need to check more Circuit Board StabilityReduce Noise and signal cross talk Improvement Key Point

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, Conclusions and Future Works 2. The Furture Works Due to contract problem,so the work of DCM have been delayed. Need to set regular schedule for interface review and technical discussion Testing and design improvement. (Need to document) Hope to get more testing information of AEP from UCB 1. Now I have finished: CDI – Testing The first version of Prototype module Some Code Testings Initial design architecture of DCM

NCKU_UCB_Tohoku ISUAL-IFR : DCM (version 1.0) March 4, The End Fu Thanks