EKT 221 / 4 DIGITAL ELECTRONICS II Chapter 0 - reVieW Sequential Logic Circuit

Introduction to Sequential Circuits Inputs Outputs Combina-tional Logic A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinatorial Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Storage Elements State Next State

Introduction to Sequential Circuits Inputs Outputs Combina-tional Logic Combinatorial Logic Next state function Next State = f(Inputs, State) Output function (Mealy) Outputs = g(Inputs, State) Output function (Moore) Outputs = h(State) Output function type depends on specification and affects the design significantly Storage Elements State Next State

Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable!

3.1 Flip-flop & Register ~ Latches ~ Edge-triggered flip-flops ~ Master-slave flip-flops ~ Flip-flop operating characteristics ~ Flip-flop applications ~ One-shots ~ The 555 timer

Introduction Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.

Introduction Latches: The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change. Flip-Flops: The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input.

Introduction Latches: S-R Latch Gated S-R Latch Gated D-Latch Flip-Flops: Edge-Triggered Flip-Flop (S-R, J-K, D) Asynchronous Inputs Master-Slave Flip-Flop Flip-Flop Operating Characteristics Flip-Flop Applications One-shots & The 555 Timer

Latches Type of temporary storage device that has two stable (bi-stable) states Similar to flip-flop – the outputs are connected back to opposite inputs Main difference from flip-flop is the method used for changing their state S-R latch, Gated/Enabled S-R latch and Gated D latch

S-R (SET-RESET) Latch Active-HIGH input S-R Latch Active-LOW input S-R Latch

Logic symbols for the S-R and S-R latch

Negative-OR equivalent of the NAND gate S-R latch

Truth table for an active-LOW input S-R latch

Assume that Q is initially LOW 1 2 3 4 5 6 7 Waveforms

Gated S-R Latch A gate input is added to the S-R latch to make the latch synchronous. In order for the set and reset inputs to change the latch, the gate input must be active (high/Enable). When the gate input is low, the latch remains in the hold condition.

A gated S-R latch

Gated S-R latch waveform: 1 2 3 4 5

Truth Table for Gated S-R Latch S R G Q Q’ 0 0 0 Q Q’ Hold 1 0 0 Q Q’ Hold 0 1 0 Q Q’ Hold 1 1 0 Q Q’ hold 0 0 1 Q Q’ hold 1 0 1 1 0 set 0 1 1 0 1 reset 1 1 1 0 0 not allowed

Gated D Latch (74LS75) The D (data) latch has a single input that is used to set and to reset the flip-flop. When the gate is high, the Q output will follow the D input. When the gate is low, the Q output will hold.

Gated S-R Latch Q output waveform if the inputs are as shown: The output follows the input when the gate is high but is in a hold when the gate is low.

Gated D Latch (74LS75)

Edge-triggered Flip-flop Logic Positive edge triggered and Negative edge-triggered All the above flip-flops have the triggering input called clock (CLK/C)

Clock Signals & Synchronous Sequential Circuits Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signal Clock Cycle Time 1 A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

Operation of a positive edge-triggered S-R flip-flop is invalid or not allowed

Example:

A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter. D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

Example:

Truth Table for J-K Flip Flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

Transitions illustrating the toggle operation when J =1 and K = 1.

Edge-triggered J-K flip-flop The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock. The small triangle on the clock input indicates that the device is edge-triggered. A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

A simplified logic diagram for a positive edge-triggered J-K flip-flop.

Example: Positive edge-triggered

Example: Negative edge-trigerred

Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

Example:

Edge-triggered flip-flop logic symbols (cont’d) The J-K flip-flop has a toggle mode of operation when both J and K inputs are high.Toggle means that the Q output will change states on each active clock edge. J, K and Cp are all synchronous inputs. The master-slave flip-flop is constructed with two latches. The master latch is loaded with the condition of the J-K inputs while the clock is high. When the clock goes low, the slave takes on the state of the master and the master is latched. The master-slave is a level-triggered device. The master-slave can interpret unwanted signals on the J-K inputs.

Basic logic diagram for a master-slave J-K flip-flop.

Pulse-triggered (master-slave) J-K flip-flop logic symbols.

Truth Table for Master-Slave J-K Flip Flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

Flip-Flop Applications Parallel Data Storage Frequency Division Counting

Flip-flops used in a basic register for parallel data storage.

J-K flip-flop as a divide-by-2 device J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

Two J-K flip-flops used to divide the clock frequency by 4 Two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.

Flip-flops used to generate a binary count sequence Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

Flip-Flop Operating Characteristics Propagation Delay Times Set-up Time Hold Time Maximum Clock Frequency Pulse Width Power Dissipation

Comparison of operating parameters for 4 IC families of flip-flop of the same type

There are several other parameters that will also be listed in a manufacturers data sheet. Maximum frequency (Fmax) - The maximum frequency allowed at the clock input. Clock pulse width (LOW) [tW(L)] - The minimum width that is allowed at the clock input during the LOW level. Clock pulse width (HIGH) [tW(H)] - The minimum width that is allowed at the clock input during the high level. Set or Reset pulse width (LOW) [tw(L)] - The minimum width of the LOW pulse at the set or reset inputs.

Basic operation of a 555 Timer Threshold Control Voltage Trigger Discharge Reset Output

Functional Diagram of 555 Timer

555 Timer as a one shot tw = 1.1R1C1 = 1.1(2000)(1F) = 2.2ms

Astable operation of 555 Timer tH = .7 (R1+R2)C1 =2.1ms tL = .7R2C1 = 0.7ms

Topics 4-1. Sequential Circuit Definitions. 4-2. Latches 4-3. Flip-flops.

Block Diagram of a Sequential Circuit

Logic Structures for Storing Information

Synchronous Clocked Sequential Circuit

Latch A type of temporary storage device. Similar to FFs because they are both bistable devices, by means of a feedback arrangement. The main difference is the method used for changing their state.

Types of Latches S-R (Set-Reset) Latch S-R Latch S-R Latch with control input D Latch Sketch the back box views for each latch..

SR Latch with NOR Gates

Logic Simulation of SR latch Behavior

SR Latch with NAND gates

SR Latch with Control Input

D Latch

Edge-Triggered Flip-flops Flip-flops are synchronous bistabe devices. Synchronous: because the output changes state ony at a certain point on a triggering input, i.e. CLK, which is the control input. Edge-triggered flip-flop: changes state at either the positive edge (rising edge) or at the negative edge (falling edge) of the cock pulse.

Types of Flip-fops Edge-Triggered Master-Slave Any more? S-R flip-flop D flip-flop J-K flip-flop Master-Slave Any more? Sketch the back box views for each flip-flop...

D-Type Positive-Edge-Triggered Flip-Flop

Positive Edge-Triggered JK Flip-Flop

Master-Slave Flip-flop Is pulse-triggered. Data is entered into the flip-flop at the leading edge of the cock pulses, but the output is only reflected at the trailing edge. Does not allow data to change while the clock pulse is still active.

Master-Slave SR Flip-Flop

Logic Simulation of a master-Slave Flip-Flop

Master-Slave JK Flip-Flop

Standard Graphic Symbols for Latch and Flip-Flops

Flip-Flop Characteristic Table

4-4 Sequential Circuit Analysis Behaviour of a sequential circuit, is determined by: The inputs. The outputs. The Present state. Flip-flops – can be any type, Logic diagram – may or may not be included.

Input equations Flip-flop input equation JA and KA : Boolean variables JA = ( XB +NY.C ) KA = ( Y.NB + C ) JA and KA : Boolean variables J and K – inputs of a JK flip-flop. Subscript A – name of flip-flop output. C – clock input. X, B and Y – inputs to combinational circuit.

Implementing Input Equations

Another Example of a Sequential Circuit DA = (AX +BX) Equations for FF inputs DB = NA.X Y = ( A+B ) . NX - Equation for output Y Subscripts A and B – names of FF outputs.

Another Example of a Sequential Circuit

State table for Circuit of Fig 4.18

Two-Dimensional State Table for the Circuit in Figure 4.18

Logic Diagram and State Table for DA

State Table for Circuit with JK Flip-Flops

State Diagram

Fig 4.21 Construction of a State Diagram

Table 4.5 State Table for State Diagram in Fig 4.21

Sequence Tables for Code Converter Example

Construction of a State Diagram

Table 4.5 with names Replaced by Binary Codes

State Table for Design Example

State Diagram for Design Example

Maps for Input Equations and Output Y

Logic Diagram for Sequential Circuit with D Flip-Flops

State table for Second Design Example

Maps for Simplifying Input Equations

Design Using D Flip-flops

Flip-Flop Characteristic Table

Flip-Flop Excitation Tables

Design Procedure using JK Flip-Flops

Maps for J and K Input Equations

Fig 4.28 Logic Diagram for Sequential Circuit with JK Flip-flops

Logic Simulation Verification for the Circuit in Fig 4.28

In-class Exercise … Referring to Fig. 4-29. Photostate Fig. 4-29. Draw guide lines for each positive clock edge, and: Identify the input values. Obtain the output values. Produce a table to list your answers in (i) and (ii). Verify these values with Table 4-11.

… In-class Exercise 2. Using the State Table as in Table 4-11, Produce 2 new columns, TA and TB. Obtain the T-FF input equations for A and B. Draw the logic diagram for this sequential circuit using T-FFs.

More Assignment Chapter 4 24, 30, 31, 33

State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition, and A label: On each circle with the output value produced, or On each directed arc with the output value produced.

State Diagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input

Example 1: State Diagram A B 0 0 0 1 1 1 1 0 x=0/y=1 x=1/y=0 x=0/y=0 Which type? Diagram gets confusing for large circuits For small circuits, usually easier to understand than the state table Type: Mealy

Moore and Mealy Models Sequential Circuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist: In contemporary design, models are sometimes mixed Moore and Mealy Moore Model Named after E.F. Moore. Outputs are a function ONLY of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs AND states Usually specified on the state transition arcs.

Moore and Mealy Example Diagrams Mealy Model State Diagram maps inputs and state to outputs Moore Model State Diagram maps states to outputs 1 x=1/y=1 x=1/y=0 x=0/y=0 1/0 2/1 x=1 x=0 0/0

Moore and Mealy Example Tables Mealy Model state table maps inputs and state to outputs Moore Model state table maps state to outputs Present State Next State x=0 x=1 Output 0 1 0 0 1 Present State Next State x=0 x=1 Output 0 1 1 0 2 2