LHCb Calorimeter Upgrade Meeting – 10th September 2012 – CERN LHCb Calorimeter Upgrade Electronics: ASIC solution status E. Picatoste, D. Gascon Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB

2 FEB Prototype Tests: 10th September 2012Calorimeter Upgrade Meeting

FEB 3 FEB Prototype Tests: Clock Tree 15th June 2012Calorimeter Upgrade Meeting WAVEFORM GENERATOR USB Clock 40MHz Trigger Signal FPGA PC with CAT sw Clock 20MHz out1out2 Clock 10MHz Clock 40MHz ANALOG MEZZANINE ADC out 12 bit x 2 channel ASICADC filter

4 ASIC Prototypes Switched integrator Track and Hold First Prototype: ICECAL chip SiGe BiCMOS 0.35um AMS 2 mm 2 Received: October chips 10th September 2012Calorimeter Upgrade Meeting Second Prototype: ICECAL2 chip SiGe BiCMOS 0.35um AMS 2 mm 2 Received: October chips

5 FEB Prototype Tests: Noise 15th June 2012Calorimeter Upgrade Meeting filter Optimize filter values for gain and noise

6 FEB Prototype Tests: Noise 15th June 2012Calorimeter Upgrade Meeting Noise measurements for one chip  With all setup  Without cable  No cable and 50Ohm termination  No chip Corrections:  Gain  Board noise Results compatible with previous measurements CalibrationsC/LSB (C) C/1LSB expected factor exp/calVo/LSB (V) 5,97109E-154,00E-151,49E+004,66E-04 Noisemeanrmsmean corrrms corrChip Noise ch237281, ,0531,7641,597 ch337841, ,6481,6961,559 ch2 CDS0,74091,321,1061,9701,713 ch3 CDS0,49891,2860,7451,9201,719 ch2 no cable37250, ,5741,2270,971 ch3 no cable37810, ,1701,2571,065 ch2 no cable CDS0,371,0360,5521,5471,201 ch3 no cable CDS0,331,0550,4931,5751,323 ch2 terminated37281, ,0531,6661,488 ch3 terminated37851, ,1411,6481,507 ch2 terminated CDS0,68091,2541,0161,8721,599 ch3 terminated CDS0,59691,3140,8911,9621,766 ch2 no chip37580,5019 ch3 no chip37590,4472 ch2 no chip CDS0,25490,6525 ch3 no chip CDS0,110,5725 Gain correction Extract board noise

7 FEB Prototype Tests: Linearity 15th June 2012Calorimeter Upgrade Meeting Measurement of linearity seems OK  Take into account the different gain due to the filter Reminder: –Low voltage measurements present high relative errors ASIC only setup ASIC+FE setup

8 FEB Prototype Tests: Plateau 15th June 2012Calorimeter Upgrade Meeting Due to clock jitter, the signal at the output must be stable (<1%) for 4 ns. Input signal AWG generated similar to clipped. Method:  Not possible to delay the 20MHz clock with the present board  Delay signal in 1ns increments  Use LEMO cable

9 DC-DC converters 15th June 2012Calorimeter Upgrade Meeting Voltage source options:  DC-DC converters  Crate voltage source DC-DC converter requires noise measurements ASIC 1.65V needs very little current. Possible solutions:  DC-DC converter  Commercial LDO or voltage reference  Use ADC Vref with a buffer COTS DC-DC Output voltage (V) DC-DC Input voltage (V) Current per ch (A) Total current (A) 3.35 (5-8) ASIC DC-DC Output voltage (V) DC-DC Input voltage (V) Current per ch (A) Total current (A) 3.35 (5-8) (5-8) ADC DC-DC Output voltage (V) DC-DC Input voltage (V) Current per ch (A) Total current (A) 3.35 (5-8)

10 September  Tests with soldered ASIC (no socket)  DC-DC noise tests  Tuneable blocks schematics  Input offset  Zin  Integrator RC  Block layout October  Meeting  Delay line (Joan Mauricio)  I2C  Chip layout and integration November  ASIC run Plans 15th June 2012Calorimeter Upgrade Meeting

11 Back-up 15th June 2012Calorimeter Upgrade Meeting

12 FEB Prototype Tests: Clock Tree 15th June 2012Calorimeter Upgrade Meeting Olivier Duarte / Thierry Caceres

13 Measurements: Noise 15th June 2012Calorimeter Upgrade Meeting cable+clipping No cable

14 Measurements: Linearity 15th June 2012Calorimeter Upgrade Meeting T/H linearity error (%) Integrator linearity error (%) V output (V) 1% 1.8 V Second Prototype simulations show: T/H linearity is lost at V out ~1.8V Cause: –Single ended limit to maximum output voltage of FDOA at the NMOS stage Possible solution: –Apply different offset to each pos/neg signal to reduce overall signal excursion All chips and subchannels tested. Linearity seems OK Reminder: –Low voltage measurements present high relative errors

15 Plateau at the integrator output Due to clock jitter, the signal at the output must be stable (<1%) for 4 ns. Input signal AWG generated similar to clipped. Method: –Delay clock signal in 1ns increments –Use LEMO cable 15th June 2012Calorimeter Upgrade Meeting