Tridas Week, November 2000Darin Acosta1 Status of the CSC Track-Finder D.Acosta, A.Madorsky, S.M.Wang University of Florida B.Cousins, J.Hauser, J.Mumford, B.Tannenbaum University of California, Los Angeles M.Matveev, T.Nussbaum, B.P.Padley Rice University A.Atamanchouk, V.Golovtsov, B.Razmyslovich, V.Sedov St. Petersburg Nuclear Physics Institute

Tridas Week, November 2000Darin Acosta2 Outline Results of CSC Track-Finder Crate Tests Future R&D Status of CSC Trigger Simulation Future Algorithm Improvements

Tridas Week, November 2000Darin Acosta3 OPTICAL SP 1 Muon Sorter 3  / port card 3  / sector ME1 ME2-ME3 ME4 SR DT TF SP Muon Port Cards MS MB1 PC From DT Track-Finder 36 Sector Receivers 12 Sector Processors To Global Muon Trigger GMT RPC 44 44 88 12 sectors (UCLA) (Florida) (Rice) (Vienna) From DT Track-Finder (Rice) Level-1 Trigger Architecture

Tridas Week, November 2000Darin Acosta4 Tests of Current Prototypes Prototypes of all Track-Finder components (except the CSC Muon Sorter) have been constructed: è Sector Processor: UFlorida è Sector Receiver: UCLA è Muon Port Card: Rice è Clock and Control Board: Rice è Channel-Link backplane: UFlorida All boards were completed in July Since the last CMS week, we have focused on completing integration tests of the complete system

Tridas Week, November 2000Darin Acosta5 Extrapolation Units XCV400BG560 Final Selection Unit XCV150BG352 Bunch Crossing Analyzer XCV50BG256 Track Assemblers 256k x 16 SRAM Assignment Units XCV50BG256 & 2M x 8 SRAM Sector Processor Prototype 12 layers 10K vias 17 FPGAs 12 SRAMs 25 buffers Florida

Tridas Week, November 2000Darin Acosta6 Sector Receiver Prototype Optical Receivers and HP Glinks SRAM LUTs Front FPGAsBack FPGAs UCLA

Tridas Week, November 2000Darin Acosta7 Track-Finder Crate Tests SPSRCCB Bit3 VME Interface Custom backplane MPC 100m optical fibers

Tridas Week, November 2000Darin Acosta8 Test Results: Sector Processor VME Interface è All LUTs and FPGA programs downloaded in less than 30s through SBS Bit3 PCI to VME interface è JTAG serialized on 25 MHz Functionality è Internal dynamic 40 MHz works with 100% agreement with ORCA simulation p 180K single muons (and 60K triple muons) p Internal FIFOs are 256 b.x. deep è Latency is 15 b.x. (not including Channel-Link input) è Firmware updated to latest (last week’s) ORCA algorithms p CSC region works flawlessly, but still working on DT/CSC overlap region è Plan to test even larger data samples (and random data) to look for any rare errors

Tridas Week, November 2000Darin Acosta9 Test Results: Sector Receiver Functionality è Three boards built and tested è Internal dynamic 40 MHz works with ORCA data and pseudo-random data p Tested 30K cycles of 256 random events è Some rare (10 -6 ) errors encountered and under study è One board with slower SRAM (10ns vs. 8ns) works fine even with 2 memories cascaded with 25 ns clock è Emulation software is similar to ORCA, but not same code p Although LUT contents were generated from ORCA

Tridas Week, November 2000Darin Acosta10 System Tests Done in Last Month Port Card  Sector Receiver è MPC and SR communicate via HP GLinks and optical fiber è Data successfully sent from input of one MPC, through 100m of optical cables, to output of SR è 1.6M random events processed with no errors Sector Receiver  Sector Processor è SR and SP communicate via Channel-Link backplane è Data successfully sent from input of one SR, through custom backplane, into the SP p Some errors encountered from unmasked inputs, but tracks were reconstructed correctly from the SR input è Successfully sent data from three SRs connected to the SP to emulate an entire trigger sector

Tridas Week, November 2000Darin Acosta11 System Tests (Continued) Port Card  Sector Receiver  Sector Processor è Successfully sent data from the input of two MPCs (representing ME2 and ME3), through one SR, and reconstructed tracks correctly in the SP è Complete chain test The Clock and Control Board prototype coordinated these tests: è Distributed clock and control signals with programmable delays è Sent BC0 to initiate tests Lots of software had to be developed (and coordinated between institutes) for these tests to happen

Tridas Week, November 2000Darin Acosta12 Future Plans: Backplane We plan to replace Channel-Link transmission as much as possible from the CSC trigger path because of its long latency (~3.5 b.x.) è In particular, for the custom point-to-point backplane in the Track-Finder crate (and probably the front-end peripheral crates) Florida proposal is to use GTLP at 80 MHz è Doubled frequency achieves 2  signal reduction (vs. 3  from Channel-Link) è Can be bussed (although we plan point-to-point) è No differential signals (fewer traces) è Can be driven by Xilinx Virtex I/O directly, or from driver chips by Fairchild and TI Prototype backplane successfully tested in Florida

Tridas Week, November 2000Darin Acosta13 GTLP Test Fixture Backplane connector Pattern generator Shift register Comparator GTLP transmitter GTLP receiver Error counter and display 50  Backplane traces (~220 mm) Clock generator (160 MHz) AMP Z-pack 2-mm 5-row Virtex, or Fairchild GTLP16612

Tridas Week, November 2000Darin Acosta14 GTLP Backplane Tests Alternating and random patterns driven up to 160 MHz with no errors 80 MHz signal 160 MHz signal Virtex Drivers Backplane traces

Tridas Week, November 2000Darin Acosta15 Future: A Compact Muon Trigger Current technology will allow us to merge all 17 FPGAs of prototype Sector Processor into just one: è Xilinx Virtex XCV2000E (~2.5M gates) available now è or Virtex 2, available soon This opens the possibility of merging the Sector Processor and Sector Receivers onto a single board è Would allow for a single crate Track-Finder (currently 6) è Reduces latency (up to 10 b.x.) è No Channel-Link connection between SR and SP è No cable to Muon Sorter è Would allow communication between sectors (through backplane) to cancel ghost tracks at boundaries è Under investigation by Florida Depends on new optical link technology to reduce connections from peripheral crate è 1.6 Gbit links with 80 MHz clock è Under investigation by Rice

Tridas Week, November 2000Darin Acosta16 Possible Board Layout

Tridas Week, November 2000Darin Acosta17 Possible Crate Layout

Tridas Week, November 2000Darin Acosta18 State of the Track-Finder Simulation It is working in ORCA ! P T assignment has been re-tuned on CMSIM118 and parameterized by a set of functions è This offers flexibility: p P T binning may be changed p 50% or 90% thresholds (or anything else) can be used è Look-up table contents are still based on integers like hardware p Contents computed dynamically Recent problem with P T assignment at  1.5 fixed è L1 Ntuples re-made thanks to Norbert è Rate under control there, but still under study in DT/CSC overlap region All SW and HW algorithms tested and agree è Modifications made to ORCA to match prototype exactly, and all LUTs used by HW generated from ORCA code

Tridas Week, November 2000Darin Acosta19 CSC Trigger Efficiency vs. Eta Any 2 stations ME1 or MB1 + any station ME1 or MB1 + any 2 stations

Tridas Week, November 2000Darin Acosta20 P T Resolution and Efficiency 5 < P T < 50 GeV 1.2 <  < % Efficiency Threshold

Tridas Week, November 2000Darin Acosta21 CSC Trigger Rate

Tridas Week, November 2000Darin Acosta22 PT Assignment Improvements Precision è Current SP prototype performs a 3-station P T measurement using a 2 MB SRAM p 27% resolution up to 35 GeV (20% for P T < 5 GeV) è Resolution can improve further with 1 or 2 more bits of precision on  23 p 22% resolution up to 35 GeV p Use larger SRAM or multiple chips è Likewise, anticipated improvements on  resolution in CLCT and SR should extend this resolution up to 50 GeV è Stronger background rejection, higher efficiency DT/CSC Overlap è Tracks bend back between MB1 and ME2 at low P T p Ambiguity in assigning P T based on  è Will investigate using  bend and  12 for P T assignment in place of 3-station measurement for this region è Won’t help tracks without MB1 p No bending between ME1 and ME2

Tridas Week, November 2000Darin Acosta23 Conclusions Prototype tests were a success (but a lot of work) It was a useful exercise to commission a crate of trigger electronics è Validates the trigger architecture è Gives us some idea of what to expect when we commission the real system è Learned of some (solvable) incompatibilities p Different VME addressing conventions p Different patterns and sorting logic than expected è Provides guidance on how to improve future boards p Additional VME registers to set board functions or to spy on intermediate data ORCA software is basically in shape for the TDR è Expected efficiency and rate reduction achieved in endcap è Still expect future improvements and tuning to occur