s Yumiko Kimezawa A design of the ECG prototype system for two leads November 5, 20101Preliminary presentation

Outline Problems Proposal Explanation of new prototype system Current state and research plan November 5, 2010Preliminary presentation2

Problems Existing prototype system - process only 1-lead not parallel not real time lower speed of processing November 5, 2010Preliminary presentation3

Proposal Existing prototype system Architecture - 1 Master core and 1 slave core Master core - Filtering process of data signals - Control of slave core Slave core - Executing the PPD algorithm for analysis ECG data signals November 5, 2010Preliminary presentation4

Proposal Existing prototype system Architecture - 1 Master core and 1 slave core Master core - Filtering process of data signals - Control of slave core Slave core - Executing the PPD algorithm for analysis ECG data signals November 5, 2010Preliminary presentation5 New idea To process multiple leads signals, filter and PPD core need to be added.

The existing prototype system November 5, 2010Preliminary presentation6 Raw ECG/EKG Data ROM Raw ECG/EKG Data ROM External Memory External Memory Graphic LCD Controller Slave CPU Slave CPU Slave CPU Memory Timer Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Shared Memory Shared Memory FIR Filter Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus

For 2-lead prototype system November 5, 2010Preliminary presentation7 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU Slave CPU Raw ECG/EKG Data ROM Raw ECG/EKG Data ROM External Memory External Memory Shared Memory Shared Memory

Explanation of new prototype system Master module - contains two filters and processes data signals like in parallel - filtered data is stored in a shared memory PPD module - two PPD cores are prepared - those core read data signals from the shared memory and execute PPD algorithm in parallel - algorithm results are stored in the shared memory execution time of each phase of the algorithm positional information of each peak of a ECG graph November 5, 2010Preliminary presentation8

Current status and research plan Understand the existing system Propose new prototype system Program control software of new system - by Nov. 30 Debug of new prototype system - by Dec. 15 Evaluation of new system by Dec. 29 November 5, 2010Preliminary presentation9