An Operating System for Reconfigurable Computers Brandon Hamilton Department of Electrical Engineering University of Cape Town Brandon Hamilton Department of Electrical Engineering University of Cape Town Supervisor – Prof. Michael Inggs (UCT) Co-supervisors – Dr. Alan Langman (SKA) Dr. Hayden So (HKU) Supervisor – Prof. Michael Inggs (UCT) Co-supervisors – Dr. Alan Langman (SKA) Dr. Hayden So (HKU)

Reconfigurable Computers CPU General Sequential Lower performance ASIC Specific Parallel High performance Programmable logic devices in a system design Hardware-based logic can be changed to perform various tasks FPGA Reconfigurable devices can be configured to provide the best match for the computational requirements at that specific time, giving much better area – speed – power performance.

Reconfigurable Open Architecture Computing Hardware

Operating Systems Access to filesystem, network Familiarity Design language independent Abstraction Scheduling Protection Access to filesystem, network Familiarity Design language independent Abstraction Scheduling Protection

Unix Process Model Hardware processes – Executing instance of gateware – Analogous to familiar Software process Active control Process management (fork/exec, process id, signals/interrupts, hierarchy) User space (multiuser, application specific, system calls) – Logical representation Abstraction Hardware processes – Executing instance of gateware – Analogous to familiar Software process Active control Process management (fork/exec, process id, signals/interrupts, hierarchy) User space (multiuser, application specific, system calls) – Logical representation Abstraction

BORPH Linux Kernel Binary File Handler (BOF) IOREG (proc filesystem) Execution Threads BORPH Hardware Interface

Hardware/Software Interface

Architecture-Dependent Code configure unconfigure reserve_hwr release_hwr get_buffer put_buffer send_buffer receive_buffer configure unconfigure reserve_hwr release_hwr get_buffer put_buffer send_buffer receive_buffer Architecture-Independent kernel code Function pointers Architecture-Dependent kernel code

Hardware Processes Execution Append BOF file to execution queue Read header Reserve available FPGA reserve_hwr Create IOREG files (/proc) Configure FPGA configure Communication Binary file handler Execution thread (bkexecd) Architecture-dependent

Read IOREG get_buffer Transfer from FPGA recv_buffer Copy from buffer to userspace put_buffer Write IOREG get_buffer Copy from userspace to buffer Transfer to FPGA send_buffer put_buffer Hardware Processes Interaction

BEE2 to ROACH BEE2 ROACH

Portability Port to NetFPGA 1 high-speed, hardware-accelerated networking systems Desktop computer running Ubuntu with BORPH kernel Port to NetFPGA 1 high-speed, hardware-accelerated networking systems Desktop computer running Ubuntu with BORPH kernel 1

Extending BORPH Smart Memory Controller – Compile time code acceleration – Perform additional processing on data access (e.g Vector processing) – Virtual Memory management – Execution switching between HW/SW Usability Low Power, High Performance Smart Memory Controller – Compile time code acceleration – Perform additional processing on data access (e.g Vector processing) – Virtual Memory management – Execution switching between HW/SW Usability Low Power, High Performance

Thank you References H. K.-H. So and R. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH," ACM Transactions on Embedded Computing Systems (TECS), Volume 7, Issue 2, Feb, 2008, New York, NY, USA. H. K.-H. So, "Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH," In Proceedings of the Sixteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machine, Apr References H. K.-H. So and R. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH," ACM Transactions on Embedded Computing Systems (TECS), Volume 7, Issue 2, Feb, 2008, New York, NY, USA. H. K.-H. So, "Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH," In Proceedings of the Sixteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machine, Apr