Arithmetic and Logic Instructions A Course in Microprocessor Electrical Engineering Department University of Indonesia

Addition-Subtraction-Comparison Whenever arithmetic and logic instruction execute, the contents of the flag register change Addition Table 5.1 illustrates the addressing modes available to the ADD instructions Register Addition Example 5.1 show a sample of register addition Immediate Addition Example 5.2 shows 8-bit immediate addition example

Addition-Subtraction-Comparison (cont’d) Memory-to-Register Addition Example 5.3 adds two consecutive bytes of data Array Addition Example 5.4 shows a procedure that adds the contents of array elements 3, 5, and 7 Example 5.5 shows the scaled-index form of addressing to add elements 3, 5, and 7 of an area of memory called ARRAY Increment Addition Examples 5.6 modifies example 5.3 to use the increment instruction for addressing NUMB and NUMB+1 (see also Table 5.2)

Addition-Subtraction-Comparison (cont’d) Addition-with-Carry Table 5.3 lists several add-with-carry instruction Figure 5.1 illustrates the addition Ex. 5.7 and Ex. 5.8 show the short program Subtraction Table 5.4 shows addressing modes for the subtraction instruction Register Subtraction Example 5.9 Immediate Subtraction Example 5.10

Addition-Subtraction-Comparison (cont’d) Decrement Subtraction It subtracs a 1 from a register or the contents of a memory location (see Table 5.5) Subtract-with-Borrow It functions as a regular subtraction, except that the carry flag (C) which holds the borrow, also subtracts from the difference (see Table 5.6 & Ex. 5.11) Comparison The comparison instruction (CMP) is a subtraction that changes only the flag bits See Table 5.7 and Example 5.12

Multiplication and Division Only modern p contain multiplication and division instructions Multiplication multiplication (bytes, words, or doublewords) can be signed integer (IMUL) or unsigned (MUL) 8-bit Multiplication The multiplicant is always in the register AL See Table 5.8 and Example 5.13 16-bit Multiplication AX contains the multiplicand and the product appears in DX-AX

Multiplication and Division (cont’d) 32-bit Muliplication The contents of EAX are multiplied by the operand specified with the instruction The product (64-bits wide) is found in EDX-EAX where EAX contains the LS32B (see Table 5.10) Division None of the flag bits change predictably; i.e., a division can result is two different types of error: an attempt to divide by zero a divide overflow (see the 3rd paragraph in p.157) In both cases, the p generates an interrupt if a divide error occurs

Multiplication and Division (cont’d) 8-bit Division The AX register stores the dividend After the division, AL contains the quotient and AH contains a whole number remainder See Table 5.11, Example 5.14 & Example 5.15 16-bit Division Instead of dividing into AX, the 16-bit number is divided into DX-AX, a 32-bit dividend The qutient appears in AX and the remainder in DX after a 16-bit division See Table 5.12 and Example 5.16

Multiplication and Division (cont’d) 32-bit Division The 64-bit contents of EDX-EAX are divided by the operand specified by the instruction, leaving a 32-bit quotient in EAX and a 32-bit remainder in EDX See Table 5.13 The Remainder After a division, the remainder could be use to round the result or dropped to truncate the result or conver-ted to a fractional remainder Study Example 5.17 and Example 5.18

BCD and ASCII Arithmetic BCD Arithmetic p allows arithmetic manipulation of both BCD and ASCII DAA (Decimal Adjust After Addition) Instruction It follows the ADD or ADC instruction to adjust the result into a BCD result (Ex. 5.19) DAS (Decimal Adjust After Subtraction) Instruction It functions as does the DAA, except that it follows a subtraction instead of an addition (Ex. 5.20)

BCD and ASCII Arithmetic (cont’d) AAA (ASCII Adjust After Addition) Example 5.21 AAD (ASCII Adjust Before Division) Example 5.22 AAM (ASCII Adjust After Multiplication) Example 5.23, Example 5.24, Example 5.25 AAS (ASCII Adjust After Subtraction) Adjust the AX register after an ASCII subtraction

Basic Logic Instruction Logic operations provide binary bit control in low-level software; allow bits to be set, cleared, or complemented AND Performs logical multiplication as depicted by the truth table in Fig.5.3 and Fig. 5.4 See also Ex. 5.26 and Table 5.14 OR Performs logical addition as depicted in Fig. 5.5 and Ex. 5.27 and Fig. 5.6 and Table 5.15 X-OR Study Fig. 5.7, Table 5.16 and Ex 5.28

Basic Logic Instruction (cont’d) Test and Bit Test Instruction Test instruction performs the AND operation; the differece is that the AND instruction changes the destination operand, while the TEST does not Test instruction affects only the flag (Table 5.17 and Example 5.29) Bit Test instruction tests single bit position (Table 5.18 and Example 5.30 NOT and NEG NOT performs logical inversion (1’s complement) and NEG performs arithmetic sign inversion (2’s complement)

Shift and Rotate Shifts Shift and Rotate instructions manipulate binary numbers at the binary bit level Shifts and Rotates find their most common application in low-level software used to control I/O devices Shifts Shifts position or move numbers to the left or right within a register or memory location Shifts also perform simple arithmetic such as multiplication by powers of 2+n (left shift) and division by powers of 2-n (right shift) Study fig. 5.9, Table 5.20, Examples 5.31 & 5.32

Shift and Rotate (cont’d) Rotates position binary data by rotating the infromation in a register or memory location either from one end to another or through the carry flag Rotates are often used to shift wide numbers to the left or right Study Fig. 5.10, Table 5.21, Example 5.33 Bit Scan Instructions BSF (bit scan forward) and BSR (bit scan reverse) scan through a number searching for the first 1-bit encountered

String Comparisons SCAS CMPS It is very powerful because allows to manipulate large blocks of data with relative ease SCAS SCAS compares the AL register with a byte block of memory (SCASB), the AX register with a word block of memory (SCASW), or the EAX register with a doubleword block of memory (SCASD) study Example 5.34 and Example 5.35 CMPS It always compares two sections of memory data as bytes (CMPSB), word (CMPSW), or doubleword (CMPSD); Study Example 5.36