lab5-1 Outline –Design a special-type synchronous sequential circuit using a counter –Schematic entry Lab 5: Counter Applications

lab5-2 Synchronous Binary Counter –A 3-stage synchronous binary counter CKQCQC QBQB QAQA MSBLSB JAJA KAKA QAQA JAJA KAKA QBQB JAJA KAKA QCQC 1 CK Output LSB Output MSB

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lab X=0,1 X=1 X=0 X=1 X=0 A more general case has a main loop S0S0 101 X=1 X=0 S1S1 S2S2 S3S3 S4S4 S5S5 S6S6

lab5-9 Design procedure: a. Use a “straight binary state assignment” for the states in the main loop. b. Use the “clear” input when transitions to state 0 are required. c. Activate the “counting function” when transitions between successive states in the main loop are required. d. Use the “load” input when transitions out of the normal counting sequence (except transitions to state 0) are required.

lab5-10 Derivation of Counter Inputs X C B AC+B+A+C+B+A x x x CLEAR LOAD D C D B D A PT x x x 1 1 x x x 1 0 x x x x x x 1 1 x x x x 0 x x x x x x x x 1 1 x x x 1 0 x x x x x x x x 0 1

lab5-11 Karnaugh maps x x BA XC Clear =A+B’+XC’ x x 1 10 x x x 1 BA XC Load =A+X+B’C’ x x x x 1 10 x x x 1 BA XC PT = X+C’ x x x x 01 x 0 x x 11 1 x x x 10 x x x x BA XC x x x x 01 x 1 x x 11 1 x x x 10 x x x x BA XC x x x x 01 x 1 x x 11 0 x x x 10 x x x x BA XC D C = BD B = 1D A = C

lab5-12 Realization D C B A D D D C D B D A CLOCK 74S163 PTPT B 1 C X’ + A’ B C X’ + A BCBC Clear Load

lab5-13 Lab Assignment –Design a synchronous counter one input x and one 3-bits state z using a counter designed in Xilinx and extra logic gates the state diagram

lab5-14 (i) Complete the hardware design of this synchronous sequential circuit using a counter, and logic gates. (ii) Draw the logic circuit diagram using schematic editor (iii) Synthesize and simulate the circuits (iv) Implement the circuits using the FPGA demo-board

lab5-15 Parts –The Parts required in this experiment are listed below: cd4rle: synchronous 4-bit binary counter with synchronous clear and load (designed in Xilinx) Cpt_di: a combinational circuit Clk1Hz: a clock with 1 Hz frequency. Seven_segment ： a module control the seven_segment displayer input requirement ： –A countdown and countup counter, depend on the input –When clock is arrive, add or subtract counter value –The top module must implemented in schematic design, cannot use verilog code