FADC Time Study EJ, HD 10/09

Purpose: to test Hai Dong’s firmware implementation of Indiana U. timing algorithm NOT meant to be a definitive study of timing resolution of the FADC250 This test uses pulse shapes that tend to enhance algorithm performance (e.g. linear leading edge, large amplitude, at least one sample at peak value) The resolution results are probably close to the best that can be done with the current algorithm

Test Setup delay 1 delay 2 delay 3 to FADC ch 6 to FADC ch 7 to FADC trigger (via TI) to FADC ch 5 Agilent 33250A Function / Arbitrary Waveform Generator to FADC ch 8 Phillips PS-715 Disc. Phillips PS-794 Gate/ Delay (delay = cable )

Part 1 Runs taken with delay values: (delay 1, delay 2, delay 3) = (1, 2, 3) ns, (1, 4, 10) ns Test with two pulse shapes having different leading edge transition rates (see Figures 1 and 2) Study all available FADC time difference distributions (in counts): (ch6 – ch5), (ch7 – ch5), (ch8 – ch5), (ch7 – ch6), (ch8 – ch6), (ch8 – ch7) Distributions are tight, with no long tails or satellite peaks (see Figures 3 and 4) Time differences are roughly what was expected for the cable delays inserted (~16 counts/ns)

Pulse 1 Figure 1.

Pulse 2 Figure 2.

SIGMA = bin = ns Figure 3.

1 bin = ns Figure 4.

Part 2 Use only ch5 and ch6 Insert precisely measured delays between ch5 and ch6 Delays measured with Stanford Research Systems Time Interval Counter (SR-620, resolution = 25 ps) Plots of FADC time difference (in counts) vs. delay show good linear behavior across a 4 ns sample bin (see Figures 5 and 6) However, the slope should not be a free parameter of the fit – it must be 16 counts/ns (250 MHz, 6-bit fine time bin) Force 16 counts/ns and only allow a common time offset Plots of (FADC time difference – delay) vs. delay show some systematic effects across a 4 ns sample bin (see Figures 7 and 8) Estimate of timing resolution: 140 ps for Pulse ps for Pulse 2

Figure 5.

Figure 6.

Figure 7.

Figure 8.