Department of Communication Engineering, NCTU 1 Instructions on Programming Programmable Array Logic Devices.

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Presentation transcript:

Department of Communication Engineering, NCTU 1 Instructions on Programming Programmable Array Logic Devices

Department of Communication Engineering, NCTU 2 1. Download Lattice ispLever, Install and Register

Logic DesignInstructions on Programming PALSau-Hsuan Wu 3

Logic DesignInstructions on Programming PALSau-Hsuan Wu 4

Logic DesignInstructions on Programming PALSau-Hsuan Wu 5

Logic DesignInstructions on Programming PALSau-Hsuan Wu 6

Logic DesignInstructions on Programming PALSau-Hsuan Wu 7

Logic DesignInstructions on Programming PALSau-Hsuan Wu 8

Logic DesignInstructions on Programming PALSau-Hsuan Wu 9

Logic DesignInstructions on Programming PALSau-Hsuan Wu 10

Logic DesignInstructions on Programming PALSau-Hsuan Wu 11 Type in your NIC

Logic DesignInstructions on Programming PALSau-Hsuan Wu 12 Type in This instruction

Logic DesignInstructions on Programming PALSau-Hsuan Wu 13 This your NIC

Department of Communication Engineering, NCTU Prepare your design with Lattice Gal20V8B

Logic DesignInstructions on Programming PALSau-Hsuan Wu 15

Logic DesignInstructions on Programming PALSau-Hsuan Wu 16

Logic DesignInstructions on Programming PALSau-Hsuan Wu 17

Logic DesignInstructions on Programming PALSau-Hsuan Wu 18 Double click to bring a dialog box

Logic DesignInstructions on Programming PALSau-Hsuan Wu 19

Logic DesignInstructions on Programming PALSau-Hsuan Wu 20 Import a file if you already have one in your project directory Otherwise, New a text file to type in your design

Logic DesignInstructions on Programming PALSau-Hsuan Wu 21

Logic DesignInstructions on Programming PALSau-Hsuan Wu 22 click this option

Logic DesignInstructions on Programming PALSau-Hsuan Wu 23 Double click the Compile Logic

Logic DesignInstructions on Programming PALSau-Hsuan Wu 24 Double click other items of Check Syntax Compiler Listing Compiled Equations Reduce Logic Reduced Equations

Logic DesignInstructions on Programming PALSau-Hsuan Wu 25 click this option

Logic DesignInstructions on Programming PALSau-Hsuan Wu 26 Double click the Link Equations

Logic DesignInstructions on Programming PALSau-Hsuan Wu 27 Double click other items of Fit Design Pro-Fit Equations Post-Fit Equations Filter Report Signal Cross Reference Create Fuse Map Chip Report JEDEC File

Logic DesignInstructions on Programming PALSau-Hsuan Wu 28 Double click the Chip Report Scroll down the lower window to see the chip layout

Logic DesignInstructions on Programming PALSau-Hsuan Wu 29 Bring this file and your GAL20V8B to Teaching Assistants for programming