CEC 220 Digital Circuit Design Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Slide 1 of 19.

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Presentation transcript:

CEC 220 Digital Circuit Design Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Slide 1 of 19

Lecture Outline Monday, November 2 CEC 220 Digital Circuit Design A multi-Function Shift-Register Counter Design Using S-R & J-K FFs Slide 2 of 19

SI Sh L Clk A Multi-Function Shift Register InputsNext StateAction Sh (Shift)L (Load) 00Hold 01Parallel Load 1XSIShift Right A multi-Function Shift-Register SO Monday, November 2 CEC 220 Digital Circuit Design Slide 3 of 19

SI Sh L Clk Sh = 0 and L = 0 Hold 0 A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 4 of 19 Sh  LL

SI Sh L Clk Sh = 0 and L = 1 Parallel Load 0 1 A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 5 of 19 Sh  LL

SI Sh L Clk Sh = 1 and L = 0 or 1 Right Shift or A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 6 of 19 Sh  LL LL

Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Recall the previous six state counter  Repeat the design using S-R flip-flops QQ+Q+ S RJ KTD 000 X X X X 0 01 Excitation Table We will need 3 FFs Slide 7 of 19

Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design State Transition Table Present State Next State XXX XXX 110XXX Present State Next State Flip-Flop Inputs XXX XXX 110XXX X XX 0X X0 XX XX 01 Present State Next State XXX XXX 110XXX X XX X XX XX X0 Present State Next State XXX XXX 110XXX X XX XX XX 01 QQ+Q+ S R 000 X X 0 Slide 8 of 19

Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design X 01XX X XX 11X1 10XX XX 110X 10XX 01 00X0 01XX X XX X 01 00X0 01XX X Slide 9 of 19

Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Circuit Design Clk Slide 10 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Recall the previous six state counter  Repeat the design using J-K flip-flops QQ+Q+ S RJ KTD 000 X X X X 0 01 Excitation Table We will need 3 FFs Slide 11 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design State Transition Table Present State Next State XXX XXX 110XXX Present State Next State Flip-Flop Inputs XXX XXX 110XXX X 0X XX 0X X0 XX XX X1 Present State Next State XXX XXX 110XXX X XX X0 X1 1X XX XX X0 Present State Next State XXX XXX 110XXX X XX 1X X1 1X XX XX X1 QQ+Q+ J K 000 X 011 X 10X 1 11X 0 Slide 12 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design X 01XX 110X 100X 01 00X0 01XX 11X1 10XX XX 11XX 10XX 01 00X0 01XX X XX 11XX 101X 01 00XX 01XX XX Slide 13 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Circuit Design Clk Slide 14 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? State Transition Table Present State Next State Flip-Flop Inputs X0X0X 001XXXXXXXXX XX01X XX1X X01X1X 101XXXXXXXXX 110XXXXXXXXX X1X0X Slide 15 of 19

Now determine how these FF input choices effects the “don’t care” state transitions Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? State Transition Table Present State Next State Flip-Flop Inputs XXX XXX XXX JKQ+Q+ 00Hold 01Reset 10Set 11Toggle Slide 16 of 19

Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? Slide 17 of 19

Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Comparing the two Designs Clk Using J-K Flip-Flops Using S-R Flip-Flops Slide 18 of 19

Next Lecture Monday, November 2 CEC 220 Digital Circuit Design VHDL in sequential logic Slide 19 of 19