Dept. of Electrical and Computer Eng., NCTU 1 Lab 9. Up Counter Presenter: Chun-Hsien Ko Contributors: Chung-Ting Jiang and Lin-Kai Chiu

Logic DesignLab 9. Up CounterChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 2 Clock Source Introduction to NE555 Circuit of NE555 The Frequency of NE555 Circuit Up Counter JK Flip-Flop Up Counter Lab 9: Up Counter

Logic DesignLab 9. Up CounterChun-Hsien Ko The IC 555 has three operating modes: Bistable mode or Schmitt trigger The 555 can operate as a flip-flop. Monostable mode The 555 functions as a "one-shot" pulse generator. Astable (free-running) mode The 555 can operate as an electronic oscillator. Dept. of Electrical and Computer Eng., NCTU 3

Logic DesignLab 9. Up CounterChun-Hsien Ko Circuit of NE555 Connect output of 555 to an inverter or AND output of 555 with signal 1 Oscillator would be more stable Dept. of Electrical and Computer Eng., NCTU 4 + -

Logic DesignLab 9. Up CounterChun-Hsien Ko The Frequency of NE555 Circuit The equation: E.g., R1=R2=470*10 3 Ω, C=10 -6 F F ~= 1Hz 555 Calculator (Website) Dept. of Electrical and Computer Eng., NCTU 5

Logic DesignLab 9. Up CounterChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 6 JK Flip-Flop

Logic DesignLab 9. Up CounterChun-Hsien Ko Falling-edge Trigger JK Flip-Flop Dept. of Electrical and Computer Eng., NCTU 7

Logic DesignLab 9. Up CounterChun-Hsien Ko Up Counter: Dept. of Electrical and Computer Eng., NCTU : 0->1 (Toggle) 2 0 : 1->0 (Toggle), carry to next digit 2 0 : 0->1 (Toggle) 2 0 : 1->0 (Toggle), carry to next digit 2 1 : 0->1 (Toggle) 2 1 : 1->0 (Toggle), carry to next digit 2 2 : 0->1 (Toggle)

Logic DesignLab 9. Up CounterChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 9 4-bits output output=input+1 at falling edge

Logic DesignLab 9. Up CounterChun-Hsien Ko Lab 9: Up Counter IC: 7476 x 2 、 7400 (NAND) x 1 、 555x1 Devices: Resistor (220Ω) x 4 、 LED x 4 、 Resistor (470KΩ) x2 、 capacitance (1μF) x1 Dept. of Electrical and Computer Eng., NCTU 10

Logic DesignLab 9. Up CounterChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 11 題外話 : 在設計電路時，應盡可能遵守只用 ” 單一時脈 ” 及 ” 不要把時脈拿來做邏輯運算 ” 二個原則，以免產生 不必要的 Bug 。 ( 除非很有把握電路不會出錯 )

Logic DesignLab 9. Up CounterChun-Hsien Ko Bonus: Design the Up Counter without T-FF Using the truth table Implement and write down the design in the report Dept. of Electrical and Computer Eng., NCTU 12 Q0Q0 Q1Q1 Q3Q3 Q4Q4 Q0+Q0+Q1+Q1+Q2+Q2+Q3+Q ……………………