TTC for NA62 Marian Krivda 1), Cristina Lazzeroni 1), Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia 3/1/20101

Content Upgrade of LTU board Upgrade of LTU front panel Upgrade of TTCex Infrastructure Software Summary 3/1/20102

Clock distribution and data flow 3/1/20103 L0 processor LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex 40 MHz clock source TTC partition TTCrx Trigger inputs For jitter < 50 ps RMS QPLL must be used ! QPLL FEE CHOKE/ ERROR Triggers Clock + Triggers

Old LTU I/Os 3/1/ pin connector 7 LVDS links 1 NIM input 2 ECL input 2 LVTTL outputs 2 ECL outputs 1 NIM output 2 LVDS inputs 4 LVDS outputs

Upgrade of LTU board 3/1/20105

Upgrade of LTU board New connectors: – CHOKE/ERROR (RJ11 – 2 LVDS in) – CHOKE/ERROR for L0 processor (RJ11 – 2 LVDS out) – BURST (Lemo – ECL, NIM in) – Warning injection (Lemo - ECL, NIM in) – 1 spare Lemo - ECL in/out + LED indication for it – 1 spare Lemo - NIM in/out + LED indication for it – All new connectors will have LEDs for indication I2C bus for reading voltages -> LTU FPGA 3/1/20106

Upgrade of LTU front panel New type of a front panel – VME64x compact. A, B (LVTTL – scope output) PLSR (ECL in), L0 (ECL out) Spare (ECL out), L0 data (ECL out) BC (ECL in) o.k., Spare (NIM out) BURST (NIM in) CHOKE/ERROR (LVDS in) CHOKE/ERROR (LVDS out) Warning injection (NIM in) Spare (ECL in/out) Spare (NIM in/out) 3/1/20107

Upgrade of TTCex Sophie Baron(CERN) has promised to push ahead this project Preliminary date is summer 2010 Preliminary cost is 3,5k CHF 9/12/200983/1/20108

Software for LTU NA62 LTU software for – Configuration and Control – Monitoring Development of LTU software has started in Bratislava: – GUI and most of the code in Java/NetBeans – part of the c code reused from ALICE 9/12/200993/1/20109

Infrastructure Each detector will be responsible to provide a optical cable (single mode, ST connector on each end) and LVDS cable (4 wires, RJ11 connector on each end) from detector to the their LTU Definition of signals BURST and Warning injection (NIM, ECL, LVDS) ??? 9/12/ /1/201010

Summary Update of LTU board and front panel almost finished Production time of LTU board is 12 weeks Cost of LTU (1,6k CHF) and cost of TTCex (3,5k CHF) should be paid AS SOON AS POSSIBLE to central BUGET in order to start the production 3/1/201011

Back up slides 3/1/201012

3/1/201013

Proposed changes for LTU New front panel VME64x compatible (ELMA 36D604-6) New connectors: CHOKE/ERROR (RJ9 – 2 LVDS in) CHOKE/ERROR for L0 processor (RJ9 – 2 LVDS out) BURST (NIM in) Warning injection (Lemo - ECL,NIM, LVDS ???) 1 spare ECL input ??? 1 spare NIM input ??? 3/1/201014

Production of LTUs for NA62 All components checked – only one component obsolete (CY7C1382B-133AC) but it is possible to buy from a grey market The production time depends on delivery of components (longest delivery is 10 weeks) plus 5-10 days manufacture The price for one LTU without any changes is 900 pounds 3/1/201015

Dictionary TTC - Timing, trigger and control LTU – Local trigger unit TTCex – TTC encoder/transmitter module TTCit – Interface Test board TTCoc – optical coupler (fan out of optical signals) 3/1/201016

TTC requirements Distribute a clock at 40 MHz Jitter < 50 ps RMS Distribute: - triggers (6 bits for each trigger) - start of burst - end of burst - event counter at the end of burst - warning ejection signals 3/1/201017

Alice LTU+TTCex+(20dB att./TTCoc) 3/1/ MHz clock source 6U VME cards 1 LTU+TTCex per detector !!! Local Trigger Unit LTU (Alice) Optical transmission of A and B channel TTCex ser. data channel A ser. data channel B Trig. data from CTP Burst clock 31 optical outputs to FEE Detector BUSY/ERROR LVDS (7) Warning ejection (WE) Monitoring of TTC TTCit TTCoc 1:32

LTU Global mode – Receive triggers from L0 processor Local mode – Emulate L0 processor - triggers (start signal can be: BC downscale, random, Pulser input) 3/1/ Serialize trigger data for TTC ch.B Encode triggers and send them to TTC Receive BUSY/ERROR from detector and propagate it to L0 processor Snapshot memory – 27 ms

LTU I/O for NA62 3/1/ pin connector 7 LVDS links 2 LVDS inputs 1 NIM input 2 ECL input 4 LVDS outputs 2 LVTTL outputs 2 ECL outputs 1 NIM output Clock input – ECL signal Pulser input – ECL input Burst input - NIM input Warning injection – LVDS input Scope probe outputs – 2 LVTTL outputs Ser. data ch.A and B - 2 ECL outputs BUSY/ERROR – LVDS input BUSY for L0 processor – LVDS output

TTCex ECL input for external clock ECL inputs for TTC channel A and channel B 10 optical outputs Incorporates encoders driven by an internal VCXO/PLL with very low jitter and can deliver the optimum optical signal level (-19 dBm) through 1:32 tree couplers to 320 destinations 3/1/201021

TTC channel B format 3/1/ bits at 40MHz, max. rate 2,5 MHz (8 data bits) 42 bits at 40MHz, max. rate 0,9 MHz (16 data bits) If 14b TTCrx ADDR == 0 => also Broadcast command/data

TTCrx chip (Broadcast data) 3/1/  2 of 8 bits already used for TTCrx internal resets

TTC format for NA62 A channel - L0 trigger: synch. signal (25ns pulse if ‘L0 accept’) B channel – L0 trigger type: asynch. message – short broadcast (6-bits info related to 25 ns pulse), Event counter at the end of burst – Start of burst, end of burst, warning ejection (a few µs before spill), warning warning ejection (1 s before spill) – short broadcast message (priority message - guaranteed time precision by inhibit interval !) 3/1/201024

Firmware upgrade for NA62 NA62 will use only short broadcast (6 bits for trigger type) !!! upgrade LTU for sending 6-bits short broadcast make inhibit interval only 400 ns - only for short broadcasts which need time precision Add input signal for Start/End of burst Add input signal for Warning injection Implement new functionality (Burst counter, …… 3/1/201025

Software for LTU NA62 LTU software for – Configuration and Control – Monitoring – L0 processor emulation Part of ALICE software may be reused 3/1/201026

Current Alice LTU software CTP emulator on LTU board Start signal for CTP emualtor Frequency Counters 3/1/201027

What do we need in the lab ? Precise clock generator ( MHz) 6U VME crate VME processor LTU module TTCex module 20 dB attenuator/TTCoc Lemo cables Single mode optical fibers Appropriate software 3/1/201028

Only reminder – there exists independent monitoring of TTC 3/1/ TTCit board - Receives data from TTCrq (TTCrx + QPLL) - Decoding of data - Display triggers and possible trigger errors on the front panel - Read snapshot memory with zero suppression via VME bus 2 LVTTL outputs for scope 1 LVDS input

Location of TTC partitions in NA62 It should be in the center in order to have similar delay to fares detectors 3 possibility: – Technical gallery – Barak with electronics directly in cavern – Control room (probably too far, necessary to make calculation how much extra delay will be there) 3/1/201030

LTU cost & time scale for production Estimation of time scale for production: Buying of components and PCB production: weeks Assembly: 2 – 3 weeks Test: weeks Estimation of cost: 3 kCHF 3/1/201031

New TTCex Advantages – new VCXO which is less expensive and available, possibility to switch off lasers which are not used First prototype – spring 2010 Production – summer 2010 Cost – 3500 CHF (500 CHF less than current TTCex) Cost can decrease if you don`t need 10 lasers (1 laser = 300 CHF) – lasers are in removable socket 3/1/201032

Summary – Distribution of Clock and Triggers – Emulation of L0 processor sequences : detectors can use it before L0 processor is available – Modification of ALICE LTU (firmware and software) – (almost) independent of L0 processor design – For beginning we can borrow a few(6 ???) TTCex from LHC experiments – New version of TTCex is better for NA62 (availability of components) – 1 LTU board (3 kCHF) + 1 TTCex (3,5 kCHF) = 6,5 kCHF/per detector (most expensive part on TTCex is laser 200 CHF/pc, so there is option to have only 1 laser assembled and use TTCoc 1:32 = 1 kCHF) -1 LTU (3 kCHF) + 1 TTCex-1laser (1,5 kCHF) + 1 TTCoc 1:32 (1 kCHF) = 5,5 kCHF/per detector -> for 32 optical receivers/FEE !!! - TTCit board(1,2kCHF) for monitoring and debugging purpose if necessary 3/1/201033

Back-up 3/1/201034

Test of max. trigger rate with LTU (Alice) board Max. trigger rate (individually-addressed frame, 16 bits data word) measured on TTCit board is 0.9 MHz 3/1/ VME Interface Local Trigger Unit LTU (Alice) FIFO ser. data channel B Data processing Optical transmission TTCex Optical receiver TTCit Optical fiber

TTC interface on LTU board 3/1/ different priorities for B channel - inhibit interval 44 BC(1,1µs) after Broadcast command request (in order to have exact time for start of burst, event reset ???) -128x32-b FIFO for trigger data (option for sw generated commands available via VME) ALICE format

3/1/ LTU (Alice)TTCex 16-pin connector 7 LVDS links 2 LVDS inputs 1 NIM input 2 ECL input 4 LVDS outputs 2 LVTTL outputs 2 ECL outputs 1 NIM output 10-optical outputs ECL I/O: 2 A-channel inputs 2 B-channel inputs 2 Encoded data outputs 2 clock outputs 1 clock input

High quality clock transmission 3/1/201038

3/1/ ALICE LTU board 16-pin connector 7 LVDS links 2 LVDS inputs 1 NIM input 2 ECL input 4 LVDS outputs 2 LVTTL outputs 2 ECL outputs 1 NIM output

3/1/ TTCex board 10-optical outputs ECL I/O: 2 A-channel inputs 2 B-channel inputs 2 Encoded data outputs 2 clock outputs 1 clock input