Report to LCFI Oversight Committee, January 2007 ■ Introduction – towards the ILC ■ Some international VXD developments ■ Progress with LCFI sensor development and testing ■ Physics studies ■ Development of readout, driver and external electronics ■ Mechanical studies ■ Finances ■ Summary 1

Introduction – towards the ILC ■ First complete costing presented at Vancouver GDE meeting, July ■ GDE now investigating ways of reducing costs. ■ Reduce amount of tunnelling needed, move DR so surrounds IPs. ■ Crossing-angles of IPs 2 mrad and 20 mrad changed to both 14 mrad so same final focus design in each case. ■ Probably only one IP, two detectors in “push-pull” mode. ■ Cost decrease ~ 30%. ■ GDE meeting at Daresbury this week at which costing will be discussed. 2

ILC developments – low power option ■ Halve number of klystrons, halving luminosity. ■ Recover L by squeezing bunches at IP. ■ Results in increased e + e  background. ■ C.f. nominal and “low P” optics, for |z| = 8 cm, B = 4T. ■ Larger BP and inner VXD radius needed, r min = 16 mm → 24 mm. ■ Leads to loss of VXD performance. ■ Increased needed to compensate, e.g. for quark charge determination: ■ LCFI studies led to rejection of “low P” optics. 3

Overview of VXD sensor technologies ■ Summary slide from Ringberg: ■ Most advanced projects probably: ♦DEPFET ♦FPCCD ♦MAPS ■ Describe status of these briefly here. 4

Alternative VXD sensor technologies – FPCCD ■ Fine Pixel CCD tackles occupancy problem (e + e  production) by increasing number of pixels, size 4.5 x 4.5  m 2, ensuring full depletion and tilting sensor to counteract Lorentz angle effects: ■ VXD design concept, two CCD sandwich with foam filling: ■ Japanese groups involved hope to obtain first CCDs from Hamamatsu this year. 5

Alternative VXD technologies – DEPFET ■ Depleted Field Effect Transistor: ■ Necessary readout speed yet to be achieved. ■ Resolution of devices studied in test beam similar to expectations for CPCCD. ■ Propose ladders with silicon “girders”. ■ In discussion with LCFI regarding mechanical studies of these sensors. ■ Hope to start test of ILC size sensors in r=15.5 mm 6

Alternative VXD technologies – MAPS ■ Monolithic Active Pixel Sensors. ■ Signal processing integrated on sensor substrate. ■ Good resolution demonstrated. ■ Studying on high speed architecture: ■ So far only multi-chip ladders constructed – stitching yet to be tested. ■ Studies of on-chip data processing starting, e.g. ADC, sparsification... ■ Readout requires “edge electronics”. 7

Progress towards decision on sensor technology ■ Programme of international reviews of ILC detector technologies proposed by World Wide Study group at Vancouver and agreed at Valencia GDE meeting, November ■ Review of VXD technology in October 2007 at Fermilab. ■ Document collecting information on all sensor technologies under study being prepared to aid VXD review process. ■ LCFI represented on steering group. ■ Regional reviews of projects continue, e.g. LCFI to be reviewed by DESY Physics Research Committee in May ■ Evaluation of VXD technologies in test beams now scheduled for

LCFI sensor development and testing – CPC2 ■ Two wafers of high speed busline- free CPC2s delivered in October. ■ All CPC2-10 passed DC tests, all CPC2-40 and one CPC-2 70 failed. ■ CPC2 and CPR2 successfully bump bonded. Capact. Struct.s CPC2-70 CPC2-40 CPC2-10 ISIS1 9

Busline free CPC2 testing ■ CPC2-10 wire bonded to mother- board with transformer drive. ■ 55 Fe X-ray signals observed at up to 45 MHz! 55 Fe source removed X-ray hits 10

Busline free CPC2 tests ■ Puzzle – efficient charge transfer with 0.4 V PP clock signals! ■ Not resonance effect. ■ Perhaps two-phase implant concentrations lower than planned? 11

Capacitance overlap measurements ■ Capacitance overlap structures being measured: ■ Will provide data on relationship between design and actual inter-gate overlap. ■ First (raw) results show evidence of non-linearity around overlap of zero. ■ Calibration and determination of gate- to-substrate capacitance needed. 12

CPC radiation hardness studies ■ 2D simulation developed using Synopsis-TCAD: ■ Count signal electrons trapped in defects in bulk silicon caused by radiation. ■ Determine Charge Transfer Inefficiency. ■ Simulation as function of frequency and temperature: ■ Verify through measurements of radiation tolerance of CPC. 13

CPC test structure design ■ Extensive CPC-T design programme with e2v now finalised. ■ Two devices study low clock amplitude operation. ■ Six devices aimed at reducing inter- gate capacitance. ■ Several of these devices are novel LCFI developments: ■ Pedestal gate CCD: 14 Not for public presentation

CPC test structure design ■ Shaped channel CCD (no two-phase implant): ■ Pedestal and Shaped Channel CCDs will be built with 20 and 24  m pitch. ■ Open Phase CCD: ■ C ig reduction could be factor for pedestal, ~ 2 for open phase CCDs. 15 Not for public presentation

ISIS2 studies ■ Demonstrated that DALSA small pixel CCDs (no gate overlap) survive irradiation to 76 krad with 60 Co, i.e. no increase in clock voltage needed to get efficient charge transfer. ■ DALSA process potentially suitable for ISIS2 manufacture. ■ Initiated design discussions with DALSA engineer, “no show- stoppers”. ■ DALSA design rules lead to imaging pixel pitch of ~ 31  m. ■ Discussions also started with ZMD, Jazz, with whom we also have non- disclosure agreements. 16 Not for public presentation

Sensor development and testing – next steps ■ Test the bump-bonded CPC2/CPR2, decide how many more assemblies needed with CPR2 or perhaps CPR2A. ■ Continue CPC2 tests using transformer drive, understand and reduce the noise. ■ Start CPC2 tests using CPD1-based motherboard. ■ Following delivery of CPC-T in April, study these structures. ■ Investigate new “proof-of-principle” p-well ISIS1. ■ Continue discussions on ISIS2 with vendors and further develop design. 17