L20 – Register Set

The 430 Register Set  Not exactly a dual ported register set, but a dual drive register set.  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU2

The MSP 430 datapath  There are two busses driving data to the ALU  There is also a MDB  There is also a MAB  Registers are 16 bit  R0,R1,R2 and R3 are special purpose register The PC, the SP, SR, and constant Any can be used as arguments in instructions and all are connected to the internal busses 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU3

Register line structure – dual ported  Diagram 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU4

The register design 430 DP  The register cell structure is somewhat less complicated as there is only one source for a new value. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU5

Still need the bus driver  The bus driver is still needed to drive the bus.  They are the same as before, but they are now 16 bits each. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU6

The bus drivers  The code  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END busdr8;  ARCHITECTURE one OF busdr8 IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= "ZZZZZZZZ";  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU7

Quartis result  The synthesis result  Resources – tri-state pins 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU8

Next assignment  The next assignment is to create a bus driver, a 4-to-16 demultiplexer, and a 16-bit register cell.  Write the VHDL code for it.  You can write a simple test bench to test it logically it you want, but most likely will wait until the register set is done to do the logic simulation. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU9

 Have a bus driver that works!!  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END busdr8;  ARCHITECTURE one OF busdr8 IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= "ZZZZZZZZ";  END IF;  END PROCESS;  END one; The new approach 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU10

Put together for four of them  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY m4drv IS  PORT (intbus : INOUT std_logic_vector(7 downto 0);  data1,data2,data3,data4 : IN std_logic_vector(7 downto 0);  dr1,dr2,dr3,dr4 : IN std_logic);  END m4drv;  ARCHITECTURE one OF m4drv IS  COMPONENT busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : busdr8 USE ENTITY work.busdr8(one);  --internal signals  BEGIN  u1 : busdr8 PORT MAP (dr1,data1,intbus);  u2 : busdr8 PORT MAP (dr2,data2,intbus);  u3 : busdr8 PORT MAP (dr3,data3,intbus);  u4 : busdr8 PORT MAP (dr4,data4,intbus);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU11

Results for bus driver  Now have no fixed 0’s 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU12

Prior results  The prior results, although they looked like they worked, didn’t.  ARCHITECTURE one OF mdrv IS  COMPONENT busdr IS  PORT (drive : IN std_logic;  data : IN std_logic;  intbus : OUT std_logic);  END COMPONENT;  FOR all : busdr USE ENTITY work.busdr(one);  --internal signals  SIGNAL dr1,dr2,dr3 : std_logic;  SIGNAL data1,data2,data3 : std_logic;  BEGIN  u1 : busdr PORT MAP (dr1,data1,intbus);  u2 : busdr PORT MAP (dr2,data2,intbus);  u3 : busdr PORT MAP (dr3,data3,intbus);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU13

The 4-to-16 multiplexer  Specification Input – 4 bit binary number Output – 16 lines numbered o0 to o15 operation is such that only 1 of the outputs is active, indicating the value of the 4-bit binary input. Input and output type – can be std_logic or std_logic_vector. Recommend using direct output generation by writing the logic equation for each output line directly from the 4-bit input. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU14

The 16-bit register cell  Write a VHDL ENTITY and ARCHITECTURE for a 16-bit register unit.  Inputs – latch – std_logic  din – std_logic_vector  Output dout – std_logic-vector 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU15

An 8 bit register  This is code for an 8-bit register – 8 F/Fs  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY reg8 IS  PORT (datain : IN std_logic_vector(7 downto 0);  load : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END reg8;  ARCHITECTURE one OF reg8 IS  BEGIN  PROCESS (datain,load)  BEGIN  IF (load='1' AND load'event) -- IF (rising_edge(load))  THEN dataout <= datain;  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU16

Another use of the register cell  The register cell will also be used for the input latching for the inputs to the ALU.  The bus driver will also be used for the output driver of the ALU result onto its bus. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU17

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU18

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU19

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU20

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU21

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU22

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU23

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU24

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU25

The objective  Dual ported register set 2 data busses Can load or drive either bus No timing – only control  To insure this unit will synthesize need to do it subcomponent by subcomponent and structurally. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU26

Why dual ported?  Traditional processor architecture  Accumulator based operation  RISC Reduced Instruction Set Computer Basis – all operations take 1 cycle Can’t achieve with an accumulator architecture Have to fetch 2 nd argument 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU27

RISC Requirements  Need to fetch both operands at once in one cycle  Dedicated instructions Load Store Functional 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU28

Synthesis results  Results in just registers  Resources – 8 registers on FPGA 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU29

2-to-1 multiplexer 8-bit  The code  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY mux2to1x8 IS  PORT (linput,rinput : IN std_logic_vector(7 downto 0);  sel : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END mux2to1x8;  ARCHITECTURE one OF mux2to1x8 IS  BEGIN  dataout <= linput when sel='0' ELSE rinput;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU30

Synthesis Results for mux 8-bit  2-to-1 mulitplexer  Resources – 8 combinational LUTs 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU31

A register line  Combine the register, the bus drivers (one for ABUS, one for Bbus), and a 2-to-1 mux for selecting which bus to have for input. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY reg_line_str IS PORT ( ABUS,BBUS : INOUT std_logic_vector (7 downto 0); aload,bload : IN std_logic; adrive,bdrive : IN std_logic; sel : IN std_logic); END reg_line_str; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU32

The code  ARCHITECTURE one OF reg_line_str IS  COMPONENT reg8 IS  PORT (datain : IN std_logic_vector(7 downto 0);  load : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : reg8 USE ENTITY work.reg8(one);  COMPONENT busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : busdr8 USE ENTITY work.busdr8(one);  COMPONENT mux2to1x8 IS  PORT (linput,rinput : IN std_logic_vector(7 downto 0);  sel : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : mux2to1x8 USE ENTITY work.mux2to1x8(one);  -- INTERNAL SIGNALS  SIGNAL muxout,regout : std_logic_vector (7 downto 0);  SIGNAL muxsel,rload : std_logic;  BEGIN  m1 : mux2to1x8 PORT MAP (ABUS,BBUS,muxsel,muxout);  muxsel <= Aload AND sel;  r1 : reg8 PORT MAP (muxout,rload,regout);  rload <= (Aload OR Bload) AND sel;  abd : busdr8 PORT MAP (adrive,regout,ABUS);  bbd : busdr8 PORT MAP (bdrive,regout,BBUS);   END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU33

The results  Synthesis results for a single dual ported register. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU34

Decoder to build a register set  Need to activate the correct register from a register set.  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY decoder2to4 IS  PORT (addr : IN std_logic_vector(1 downto 0);  sel_line : OUT std_logic_vector(3 downto 0));  END decoder2to4;  ARCHITECTURE one OF decoder2to4 IS  BEGIN  sel_line(0) <= NOT addr(1) AND NOT addr(0);  sel_line(1) <= NOT addr(1) AND addr(0);  sel_line(2) <= addr(1) AND NOT addr(0);  sel_line(3) <= addr(1) AND addr(0);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU35

Decoder synthesis  Synthesis gives  Resources – pins and 4 combinaltional LUTs 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU36

A full register set  A full register set would have at least 8 registers. Here will start with 2 registers. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU37

The code  Have all the reference unit code.  The first time abbreviated ENTITY interface – only the busses. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY reg_set_2 IS PORT (ABUS,BBUS : INOUT std_logic_vector(7 downto 0)); END reg_set_2; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU38

The 2 register architecture  ARCHITECTURE one OF reg_set_2 IS  -- this architecture is to confirm the build up of bus units  COMPONENT reg_line_str IS  PORT (ABUS,BBUS : INOUT std_logic_vector (7 downto 0);  aload,bload : IN std_logic;  adrive,bdrive : IN std_logic;  sel : IN std_logic);  END COMPONENT;  FOR all : reg_line_str USE ENTITY work.reg_line_str(one);  -- now delcare signals for test setup  SIGNAL aload1,bload1,adrive1,bdrive1,sel1 : std_logic;  SIGNAL aload2,bload2,adrive2,bdrive2,sel2 : std_logic;  BEGIN  r1 : reg_line_str PORT MAP (ABUS,BBUS,aload1,bload1,adrive1,bdrive1,sel1);  r2 : reg_line_str PORT MAP (ABUS,BBUS,aload2,bload2,adrive2,bdrive2,sel2);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU39

Quartis results  After synthesis  Report usage only shows pins – you have to traverse into each unit to get resources. Can see these by running cursor over the unit in the RTL viewer. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU40

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU41

Usage summary by using cursor  For each register line 32 buffers (regular) 2 combination ANDs 1 combination OR 8 DFF 16 Tri-state buffers 8 muxes 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU42

Expanding register line unit  Pushing down by double clicking in unit box  The same unit from before 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU43

Now moving control signals  Move the control signals to the ENTITY. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU44

The last step  Adding a decoder to generate the selects  This time a 1-to-2 decoder  Then a bunch of errors popped up so back up. Do the implementation one step at a time Add the regno signal to the ENTITY  WORKED FINE Add the decoder COMPONENT – re-synthesize  WORKED FINE Add and instantiation for the decoder  WORKED FINE Finally link the decoder output to the select lines with concurrent signal assignment statements. It then started generating errors so starting a new approach. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU45

Build up from drivers  The architecture – Diagram not complete 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU46

The units  The tri-state bus drivers 4 of them 8-bits each in a hierarchical unit  The registers 4 of them as instantiated units  Mux2to1x8 – a byte width 2 to 1 multiplexer used to select which input to have available to load into register, the ABUS or the BBUS  Decoders 2 to 4 – takes the 2 bit register number and generates the correct select line – used for selecting which register to load from the ABUS or BBUS and which register to drive. Note that the system can drive just register. It is capable of two operations each cycle.  Glue logic – generated the load and drive signals. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU47

Results for the design  Resources Pins – 24  ABUS – 8  BBUS – 8  aload,bload,adrive,bdrive – 4  aregno,bregno – 2 each – 4 Registers – 32 (4 registers 8-bits each) Combinational LUTs – 60  Average fanout – /2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU48

Synthesis results  Quartis produced graphic 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU49

Pushing down  Decoder register and mux 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU50

Next step  The next step is the VHDL simulation of the register set to be sure its behavior is as desired. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU51

Lecture summary  Have seen how to create a 4 register location register-set.  The next assignment is to use the code here (which is also on the web page) to generate a 8 location register. Simply build upon this code. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU52