MEG trigger system This short presentation describes the present status of the trigger algorithms of the MEG experiment implemented on the Xilinx FPGA XCV812E. The project version is Ver.1 Rev.10. This project is designed by using the schematic entry of Xilinx software package “Foundation 4.1”. The design is hierarchical. There are two top level schematics: MEG2MAIN : it contains the data in/out buses and the processing MACROs.MEG2MAIN MEG2INT : it contains the control and interface signals as well as the control and readout MACROs.MEG2INT

inputs input cyc.mem. / mux INPMT_BLOCK INPMT_BLOCK processing algorithms PMFOURWHOLE PMFOURWHOLE final processing ALLPMT ALLPMT LVDS cyc.mem. / mux LVDS_BLOCK LVDS_BLOCK outputs MEG2MAIN trigger control TRIG_BLOCK PMT signals LVDS in LVDS out spare out

mux PMT_MUX PMT_MUX cyclic memories PMT_FIFO PMT_FIFO INPMT_BLOCK

PMT_FIFO cyclic memories dual port RAMS cyclic address CoreGen module: bus multiplexer Storing of the sampled signals or buffers available for testing purposes

PMT_MUX CoreGen modules: bus multiplexer Choice between the sampled signals or the cyclic memories stored data

signal time NN_ONE_PMT_TIME NN_ONE_PMT_TIME maximum charge MAX_FOUR_PMT MAX_FOUR_PMT charge sum SUM_FOUR_PMT SUM_FOUR_PMT lut & ped ONE_PMT_BLOCK ONE_PMT_BLOCK PMFOURWHOLE CoreGen module: bus multiplexer

ONE_PMT_BLOCK pedestal subtraction ONE_PMT_SUBPED ONE_PMT_SUBPED look up tables dual port RAMS Correction for different PMT gain and non-linearity

ONE_PMT_SUBPED delay sum of 4 pulses pedestal threshold enable pedestal pedestal subtracted signal sample CoreGen module: subtract CoreGen modules: adders CoreGen modules: adder & comparat. CoreGen module: parallel shift register

MAX_FOUR_PMT sum of 4 PMT samples max amplitude signal SUM_FOUR_PMT CoreGen modules: adder CoreGen modules: comparator CoreGen modules: mux corresponding PMT index

NN_ONE_PMT_TIME

ALLPMT final information: sum of 16 PMT samples final information: time of the max amplitude PMT CoreGen modules: adder final information: max amplitude signal (divided by 2) final information: corresponding PMT index CoreGen modules: comparator CoreGen modules: mux CoreGen modules: par. shift register CoreGen module: mux

LVDS_BLOCK CoreGen modules: mux cyclic memories LVDSFIFO LVDSFIFO LVDS output cyclic memory LVDS input cyclic memory final cyclic memory Choice between the elaborated signals or the cyclic memories stored data cyclic memories LVDSFIFO4 LVDSFIFO4

LVDSFIFO cyclic memories dual port RAMS cyclic address CoreGen module: bus multiplexer Storing of the transmission infp (48 bits) or buffers available to test data transmission

LVDSFIFO4 cyclic memories dual port RAMS cyclic address CoreGen module: bus multiplexer Storing of the final information (50 bits)

MEG2INT control signals FPGA startup readout inputs spare in/out connections signals to status LED FPGA control MEG2_CTRL MEG2_CTRL

CoreGen modules: decoders address decoder CoreGen modules: registers control registers address readout CoreGen modules: mux tri-state bus cyc.mem. readout CoreGen modules: decoders readout mux driver runmode selection MEG2_RUMO

MEG2_RUMO runmode signal go to stop_mode go to run_mode 100 MHz clock