24th October 2003 M. Noy, Imperial College London0 M. Noy FED Project Status

24th October 2003 M. Noy, Imperial College London1 Tracker Readout Chain To DAQ interface (VME and SLINK)

24th October 2003 M. Noy, Imperial College London2 First FED Prototype (Jan 2003) “Primary” Side OptoRx CFlash VME64x 9U board 34 x FPGAs Analogue TTC FE Unit Power Memories 96 channels JTAG

24th October 2003 M. Noy, Imperial College London3 FED Architecture and Interfaces  Modularity  9U VME64x Form Factor  Modularity matches Opto Links  8 x Front-End “modules”  OptoRx/Digitisation/Cluster Finding  Back-End module / Event Builder  VME module / Configuration  Power module  Other Interfaces:  TTC : Clk / L1 / BX  DAQ : Fast Readout Link  TCS : Busy & Throttle  VME : Control & Monitoring  JTAG : Test & Configuration

24th October 2003 M. Noy, Imperial College London4 FED Firmware Overview Effort concentrated at RAL Development based on the FED URD Functionality to include Timing synchronisation features (fine and coarse) APV25 data frame header finding Pedestal and common mode subtraction Zero-suppression/clustering Event formatting Readout interface; VME and SLINK-64 Emphasis to provide initial requirements first (P. G. Verdini) Large Scale Assembly tests require a subset of the above

24th October 2003 M. Noy, Imperial College London5 Firmware Status Initial requirements completely fulfilled: Timing synchronisation features (fine and coarse) APV25 data frame header finding  Pedestal and common mode subtraction – present but untested  Zero-suppression/clustering – present but untested Event formatting Readout interface – VME only

24th October 2003 M. Noy, Imperial College London6 FED Software Overview Project split between IC and RAL RAL responsibility: Low level ‘Hardware Access Routines’ IC responsibility: ‘User Interface’ and XDAQ wrapper Designed to integrate into existing test beam environment Coordination led from within IC Close collaboration with existing tracker DAQ group at CERN Integration test planned for beginning Nov

24th October 2003 M. Noy, Imperial College London7 Current FED Software Status RAL Status Low level software and firmware debug/development efforts coordinated Library is functional and extensively debugged Effort continues to ensure reliability of operation IC Status Interface to online software framework largely complete and under test Recent effort to integrate IC/RAL libraries made good progress User interface layer in use

24th October 2003 M. Noy, Imperial College London8 Analogue Performance Effort concentrated at IC Prototype test bench Preliminary results presented at July 2003 Tracker Week A few surprises still under investigation FED is working, but there will be some minor changes New test bench under development Multi-channel tester (G. Iles and Co.) 24 per board + scalable clock and trigger dist. Step towards production testing system

24th October 2003 M. Noy, Imperial College London9 Multi Channel FED Tester DACs Fibre reels 8-way MU optical connectors Clks provided via QPLLs Analogue Optical Hybrids Cross-point switches VME interface System control FPGA G. Iles & Co.

24th October 2003 M. Noy, Imperial College London10 FED Noise Performance RMS noise for every channel measured Max of FED ~ 1.1 ADC counts Equivalent to 350e - (including OptoRX) Strange feature on each 5 th channel Probably a layout issue, but not a serious one Peak RMS noise as a function of channel number OptoRX Present on Ch0-23

24th October 2003 M. Noy, Imperial College London11 Fine Clock Skewing Fine skew adjustment Individual skew for every channel Spans entire clock period in 32 steps Slightly non-linear shifts, but nothing problematic

24th October 2003 M. Noy, Imperial College London12 FED Pulse Shaping Issues An unexpected undershoot was seen before the pulse Approximately 5% of peak size Width ~10ns, but suppression of peak was also seen Eliminated most questions of layout by direct probing on the FED Tied down to the ADC: Analog Devices part AD9218 FED Channel Emulator was implemented Used Analog Devices Evaluation board Effect reproducible:

24th October 2003 M. Noy, Imperial College London13 FED Pulse Shaping Issues Undershoot developed here by the AD9218 Effect not present on scope Un-optimised pulse shape from a FED channel emulator test bench: NOT FROM THE FED

24th October 2003 M. Noy, Imperial College London14 PRELIMINARY Undershoot Solution: On FED It was found that the problem disappeared in 1Vpp mode Analog Devices design engineer has confirmed by simulation that the effect is due to the way the device operates in 2Vpp mode Quantitatively consistent results For the FED: Requires the changing the ADC mode, and introducing a gain of 0.5 before the ADC Two ways of doing this: both under investigation now:

24th October 2003 M. Noy, Imperial College London15 FED Project Schedule FEDs for Large Scale Assembly Tests (restricted functionality) 1 - Oct 03; 2 – end of 2003; 2 – beginning of 2004; 6 – mid 2004 FED Pre-production manufacture, Q With full firmware/software functionality FEDv2 hardware iteration FEDv3 (~500)FEDv2 (“20”)FEDv1 (“10”) DesignTest Pre- Production & Installation

24th October 2003 M. Noy, Imperial College London16 Procurement History Two boards produced in Jan 2003 without OptoRX SER001 at IC with 2 (/8) OptoRX (HRX9003) Analogue evaluation SER002 at RAL without OptoRX fitted electrical tests and firmware development Three boards assembled June SER005 with 8 OptoRXs Only minor problems seen on these 5 boards SER006 – 011 arrived beginning Oct 2003 Tin finish used due to better long term stability of the coating Waited for ATLAS verification that the tin finish worked First batch to be assembled fully including OptoRX devices

24th October 2003 M. Noy, Imperial College London17 Manufacturing Issues SER all exhibited shorts between Vcc and Gnd Batch arrived 8 th October PCB company claims boards passed pre-plating tests There were no BGA related problems on SER One board returned to assembly company (10 th Oct) X-ray imaging showed problems under largest FPGAs (VII 1500kGate) All large FPGAs removed from one FED RAL confirmed that shorting problem disappeared

24th October 2003 M. Noy, Imperial College London18 X-RAY Image XC2V1500 / FPGA Note: tracks between vias and caps are not visible Example of solder bridges potential shorts between power and Gnd pins Components ok

24th October 2003 M. Noy, Imperial College London19 Action by RAL and AC Board returned to the assembly company and all large FPGAs replaced (with new parts) The board returned to RAL, and was powered on the bench successfully Vcc-Gnd shorts have been repaired Subsequent boundary scan tests Show ~10 connection errors on 2 (/24) Delay FPGAs (40kGate) Errors concentrated on one, but both have to be replaced Possible Explanation: Migration of solder balls caused by PCB finish in use this time Problem not fully understood/debugged yet

24th October 2003 M. Noy, Imperial College London20 Summary FED Firmware Provision of initially required reduced functionality progressing well FED Online Software Debugging and integration of FED libraries underway Software close to completion and compatible with existing test beam framework FED Performance Analogue performance meets requirements to date Main pulse shaping issue solutions under evaluation Advanced test bench under development Procurement and Manufacture Made fast positive steps towards understanding the manufacturing problems Tendering under investigation for pre-production and final manufacture First FED to CERN week 45 (3 rd Nov. 2003) Integration (sw/hw) to start then