CEC 220 Digital Circuit Design Programmable Logic Devices

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Presentation transcript:

CEC 220 Digital Circuit Design Programmable Logic Devices Friday, February 21 CEC 220 Digital Circuit Design

CEC 220 Digital Circuit Design Lecture Outline Programmable Logic Devices PLA: Programmable Logic Array PAL: Programmable Array Logic CPLD: Complex Programmable Logic Devices FPGA: Field Programmable Gate Arrays Friday, February 21 CEC 220 Digital Circuit Design

Programmable Logic Devices Programmable Logic Array (PLA) A PLA implements a SOP type expression Inputs Outputs Friday, February 21 CEC 220 Digital Circuit Design

Programmable Logic Devices Programmable Logic Array (PLA) F0 F1 F2 F3 Short-hand notation so we don't have to draw all the wires! Implement the functions Friday, February 21 CEC 220 Digital Circuit Design

Programmable Logic Devices Programmable Array Logic (PAL) What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)? PAL - Constrained topology of the OR Array A given column of the OR array has access to only a subset of the possible product terms Friday, February 21 CEC 220 Digital Circuit Design

Programmable Logic Devices Programmable Array Logic (PAL) Implement a full adder using a PAL Cout S Cin Friday, February 21 CEC 220 Digital Circuit Design

Complex Programmable Logic Device (CPLD) Architecture of an Altera XCR3064l CPLD 64 of these blocks are in this chip The newer Altera Max V parts have 1,700 blocks Friday, February 21 CEC 220 Digital Circuit Design

Field Programmable Gate Array (FPGA) Typical layout Configurable Logic Block Lookup Table Friday, February 21 CEC 220 Digital Circuit Design

Field Programmable Gate Array (FPGA) Current Xilinx FPGA Offerings Friday, February 21 CEC 220 Digital Circuit Design

CEC 220 Digital Circuit Design Next Lecture Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design