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8 Class of Service Distribution SW/HW interface Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration Clusters of VPUs Clusters of VPUs Clusters of VPUs LBS Arbitration

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S/W emulator or H/W DSP system Input vectors Output reports LBS1 Classifier Stratix II 180 PROCStar II 14 PCI Bus DDR2 LBS2 DDR2 LBS3LBS4 Main Bus : Data In and Controls Stratix II 180 Ring Bus Per LBS registers

Right Bus Reports NIOS VPU Main Bus Input Vectors Load Balancing Switch (LBS) Left Bus Muxed Reports NIOS VPU DDR2 A FIFO IN Data and Controls Stratix II FPGA DDR2 B FIFO OUT NIOS VPU 15 Bus Control Block

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Load Balancing Switch (LBS) DDR2 Controls Bank A LBS 1-4 Stratix II 180 FPGA DDR2 Controls Bank B I/O – LBS Control Block Data flow NIOS cluster 24 Bus Control Block

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27 Header Data 1 to N of 32-bit Words Tail …… Unused Nios Number Data Length NVector ID/Command Type 8-bit32-bit16-bit Version 4-bit SW/HW Control 1-bit Type 1-bit (Data/Command)

PCI Main Controller unit Stratix II FPGA Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System Control FIFO Input Port FIFO Output Port Control Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter 28

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33 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statis tics Repo rter

34 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statis tics Repo rter

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37 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter

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40 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter

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| |0 1 2|1 0 1|7 0 0|0 0 14|3 0 15|0 1 4|7 1 3| | Status input Dynamic port mapping RR on Active ports Next port Static Priority/ Aging mapping

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45 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter Statistics Reporter

46 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter Statistics Reporter

47 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter Statistics Reporter

48 Main Controller unit Output Writer Input Reader FIFO Input Port FIFO Output Port Muxed output data bus Input data bus Control and Status Statistics Reporter

49 Main Controller unit Output Writer Cluster Arbiter NIOS II System Input Reader Cluster Arbiter NIOS II System FIFO Input Port FIFO Output Port Cluster Arbiter NIOS II System Muxed output data bus Input data bus Control and Status Statistics Reporter Statistics Reporter

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63 Module ModuleLogicutilization% Memory (M4K) % Peripheral IPs (MegaFIFO, PLLs, etc.) 3, User System (All VPUs + LBS)42, Single VPU6, LBS Logic1, Total usage of chip resources 45, Total available 143, VPU resource usage is based on basic VPUs and may be decreased by advanced configurations and policies.

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65System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) VPUs Classes of 6 VPUs Classes of 6 VPUs Classes of 6 VPUs VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

66System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) VPUs Classes of 6 VPUs Classes of 6 VPUs Classes of 6 VPUs VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

67System Time of Service[sec]Throughput[Mbit/s]Impr SW (on Core2Duo E6600) One VPU VPUs Classes of 6 VPUs Classes of 6 VPUs Classes of 6 VPUs VPU performance is based on basic VPUs and RR arbitration and may be increased for giving workload after perf. analysis by defining advanced configurations and policies.

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