Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Basics of register-transfer design: –data paths and controllers; –ASM charts.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Register-transfer design n A register-transfer system is a sequential machine. n Register-transfer design is structural— complex combinations of state machines may not be easily described solely by a large state transition graph. n Register-transfer design concentrates on functionality, not details of logic design.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Register-transfer system example A register-transfer machine has combinational logic connecting registers: DQ combinational logic DQDQ combinational logic combinational logic

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Block diagrams Block diagrams specify structure: wire bundle of width 5

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Register-transfer simulation n Simulates to clock-cycle accuracy. Doesn’t guarantee timing. n Important to get proper function of machine before jumping into detailed logic design. (But be sure to take into account critical delays when choosing register-transfer organization.)

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Simulation coding n Hardware description languages are typically supported by a simulation system: VHDL, Verilog, etc. –Simulation engine takes care of scheduling events during simulation. n Can hand-code a simulation in a programming language. –Must be sure that register-transfer events happen in proper order.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Sample VHDL code sync: process begin wait until CLOCK’event and CLOCK=‘1’; state <= state_next; end process sync; combin: process begin case state is when S0 => out1 <= a + c; state_next <= S1;... end process combin; sync process models registers combin process models combinational logic

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Sample C simulator while (TRUE) { switch (state) { case S0: x = a + b; state = S1; next; case S1:... } loop executed once per clock cycle each case corresponds to a state; sets outputs, next state

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Data path-controller systems n One good way to structure a system is as a data path and a controller: –data path executes regular operations (arithmetic, etc.), holds registers with data- oriented state; –controller evaluates irregular functions, sets control signals for data path.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Data and control are equivalent n We can rewrite control into data and visa versa: –control: if i1 = ‘0’ then o1 <= a; else o1 <= b; end if; –data: o1 <= ((i1 = ‘0’) and a) or ((i1 = ‘1’) and b); n Data/control distinction is useful but not fundamental.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Data operators n Arithmetic operations are easy to spot in hardware description languages: –x <= a + b ; n Multiplexers are implied by conditionals. Must evaluate entire program to determine which sources of data for registers. n Multiplexers also come from sharing adders, etc.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Conditionals and multiplexers if x = ‘0’ then reg1 <= a; else reg1 <= b; end if; code register-transfer

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Alternate data path-controller systems controller data path one controller, one data path controller data path controller data path two communicating data path-controller systems

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR ASM charts n An ASM chart is a register-transfer description. n ASM charts let us describe function without choosing a partitioning between control and data. n Once we have specified the function, we can refine it into a block diagram which partitions data and control.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Sample ASM chart

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR ASM state n An ASM state specifies a machine state and a set of actions in that state. All actions occur in parallel. s1 x = a + b y = c - d + e o1 = 1 name of state (notation only)

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Actions in state n Actions in a state are unconditionally executed. n A state can execute as many actions as you want, but you must eventually supply hardware for all those actions. n A register may be assigned to only once in a state (single-assignment rule).

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Implementing operations in an ASM state state with one addition two additions requires two adders

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Sequences of states n States are linked by transitions. n States are executed sequentially. Each state may take independent actions (including assigning to a variable assigned to in a previous state). s1 x = a + b s2 x = c + d y = a + d

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Data paths from states n Maximum amount of hardware in data path is determined by state which executes the most functionality. n Function units implementing data operations may be reused across states, but multiplexers will be required to route values to the shared function units.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Function unit sharing example mux allows + to compute a+b, a+c

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Conditionals n Conditional chooses which state to execute next based on primary input or present state value. n Can be drawn in either of two ways: a = b x T F

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Execution of conditionals n An ASM chart describes a Moore sequential machine. If the logic associated with an ASM chart fragment doesn’t correspond to a legal sequential machine, then it isn’t a legal ASM chart. n Conditional can evaluate only present state or primary input value on present cycle.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Implementing an ASM branch in a Moore machine ASM chart state transition graph of controller

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Mealy machines and ASM n Mealy machine requires a conditional output. n ASM notation for conditional output: i1 0 y = c + d

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Extracting data path and controller n ASM chart notation helps identify data, control. n Once you choose what values and operations go into the data path, you can determine by elimination what goes into the controller. n Structure of the ASM chart gives structure of controller state transition graph.

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Data path-controller extraction