DAC 2006 Sponsored by: Moderated By John Blyler, Editor, Chip Design Magazine Moderated By John Blyler, Editor, Chip Design Magazine

DAC’06 Reining in time-to-market for next-generation embedded designs 1/26/ My Background BS Engineering Physics, MS EE (Digital and RF) Engineering Background –18 years, complex hardware-software systems Teaching Background –Affiliate Professor – PSU, Systems Engineering –Short courses for NSA on Technical Risk Assessment Print/Online Media Background –Editorial Director: Chip Design magazine ( Embedded Intel magazine ( Design Trends Reports – Sep ’ 06 –Previously: Senior Tech Editor – Wireless Systems mag Freelance, Edutopia magazine and others Associate Editor, IEEE I&M magazine Book author, IEEE Press Contact: (503)

DAC’06 Reining in time-to-market for next-generation embedded designs 1/26/ Embedded Designs: Broad Challenges At 65nm Chip Design mantra: –Power, Performance, Area and Cost Power and Performance –Key technical parameters Area and Cost –Drivers for deeply embedded, high volume consumer market –$1.25 billion units by 2008

DAC’06 Reining in time-to-market for next-generation embedded designs 1/26/ nm Issues with Implementing Embedded Processor Designs: Deeply embedded CPU system –Performance must balance cost Proven solution –Shrink geometries (65nm) –Lower power, increase performance, lower area –But increase complexity Bus centric and multiple core-memory architectures At submicron designs: –Proven reference methodology –Lots of IP

DAC’06 Reining in time-to-market for next-generation embedded designs 1/26/ Today’s Panel Discussion Flow Chartered Semi: Nanometer flow for today’s designs ARM PIPD: Supporting processes with library development and qualification ARM: New and upcoming processor architectures Magma: Importance of reference methodologies Broadcom: Actual implementation of reference methodology and Cortex R4 processor Followed by Q&A and more.