August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 1 WWiSE Group Partial Proposal on Turbo Codes August 13, 2004 Airgo Networks, Bermai, Broadcom, Conexant, STMicroelectronics, Texas Instruments

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 2 WWiSE contributors and contact information Airgo Networks: VK Jones, Bermai: Neil Hamady, Broadcom: Jason Trachewsky, Conexant: Michael Seals, STMicroelectronics: George Vlantis, Texas Instruments: Sean Coffey,

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 3 Contents Overview of partial proposal Motivation for advanced coding Specification of turbo code Performance results Summary

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 4 Overview of partial proposal The WWiSE complete proposal contains an optional LDPC code to enable maximum coverage and robustness FEC coding fits into the system design in a modular way, and in principle any high-performance code could be used instead of the LDPC code This partial proposal highlights an alternative choice for optional advanced code –The system proposed is identical to the WWiSE complete proposal in all respects except that the optional LDPC code is replaced by the turbo code described here

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 5 Motivation for advanced coding Advanced coding translates into higher achievable throughput at the same robustness In particular, in most configurations the BCC of rate ¾ and turbo code of rate 5/6 have approximately the same performance Thus advanced coding enables a rate increase from ¾ to 5/6 without robustness penalty At any given rate, advanced coding enhances coverage and robustness In addition, the modularity of the design means that the advantages carry over to every MIMO configuration and channel bandwidth

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 6 Transmitter block diagram Turbo encoder, puncturer MIMO interleaver Symbol mapper Add pilots D/A Interpol., filtering, limiter Upconverter, amplifier IFFT Add cyclic extension (guard)

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 7 Turbo encoder Parity bit 0 Parity bit 1 1+D +D 3 1+D 2 +D 3 g(D) = Turbo interleaver 1+D +D 3 1+D 2 +D 3 g(D) = Systematic bit These are the constituent codes used in the 3GPP/UMTS standard encoder

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 8 Turbo code frame format The data payload is padded to reach a multiple of 512 bits The result is divided into blocks of 2048 bits and 512 bits –Number of 512 bit blocks is in the range 1-4 All 512 bit blocks are placed at end of frame Each block is encoded as a separate turbo codeword

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 9 Turbo interleaver design Two interleavers are proposed, one for each supported block size: 2048 and 512 bits Each interleaver is a contention-free inter-window shuffle interleaver –Designed to minimize memory contention when code is decoded in parallel –Equivalent performance to 3GPP/UMTS interleavers

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 10 Puncturer Parity bits are punctured at regular intervals –Puncture intervals: Systematic & tail bits are not punctured; pad bits are punctured All code rates are easily derivable from mother code Other puncturing patterns and setups also work well Code ratePuncture interval 2/34 3/46 5/610

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 11 Puncturing tail codewords Tailing codewords, i.e., codewords of length 512 information bits, are punctured differently, to a lower code rate –This facilitates low latency decoding: tail codeword blocks are shorter and can be decoded with fewer iterations, without affecting operating point Puncture intervals for tail blocks: Code ratePuncture interval 2/32 3/43 5/63

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 12 Parallelization of turbo decoders Parallelization: –Divide trellis into a number of (possibly overlapping) segments and decode each in parallel –Any reasonable number of iterations can be achieved without affecting latency End-of-packet latency: –To achieve full gains of turbo or any iterative code, it is possible to taper codeword length and rate at end of packet –High throughput naturally requires longer packets and Block Ack Block 1 Block 2 Block 3...

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 13 Complexity Compare to state complexity of 64-state BCC decoding equivalent throughput System assumptions: M-state constituent codes, I iterations, soft-in soft-out algorithm extra cost factor of , BCC duty factor of  Decoder must process 2 x 2 x I x  trellis transitions (I iterations, 2 constituent codes, forward-backward for each, less duty factor), each of which costs  M/64 as much –Overall complexity is 4I  M/64 times as much as 64-state code –E.g., with M = 8, I = 7,  = 1.5,  = 0.7, we have times the state complexity –This does not account for other differences such as memory requirements and interleaver complexity

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 14 Performance results

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 15 Simulation setup All combinations of: –Channels B, D, AWGN –20 MHz and 40 MHz –Rate ¾ and rate 5/6 –BCC and turbo code All simulations under ideal conditions

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 16 Channel model B NLOS, 20 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 17 Channel model B NLOS, 40 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 18 Channel model D NLOS, 20 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 19 Channel model D NLOS, 40 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 20 AWGN, 20 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 21 AWGN, 40 MHz

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 22 References IEEE documents: IEEE / n, “WWiSE group PHY and MAC specification,” M. Singh, B. Edwards et al. IEEE / n, “WWiSE proposal response to functional requirements and comparison criteria,” C. Hansen et al. IEEE / n, “WWiSE partial proposal on turbo codes: specification,” S. Pope et al. Parallelization: 4. K. Blankenship, B. Classon, and V. Desai, “High-throughput turbo decoding techniques for 4G,” Int. Conf. on 3G Wireless & Beyond, E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Communications Magazine, August 2003, pp

August 2004 doc.: IEEE /0951r1 Submission S. Coffey, et al., WWiSE group Slide 23 References, contd. 6. Z. Wang, Z. Chi, and K. K. Parhi, “Area-efficient high-speed decoding schemes for turbo decoders,” IEEE Trans. VLSI Systems, vol. 10, no. 6, pp , Dec S. Yoon and Y. Bar-Ness, “A parallel MAP algorithm for low latency turbo decoding,” IEEE Communications Letters, vol. 6, no. 7, pp , July 2002 Interleavers: 8. A. Nimbalker, K. Blankenship, B. Classon, T. Fuja, and D. Costello, “Inter-window shuffle interleavers for high-throughput turbo decoding,” Proc. Int. Symp. on Turbo Codes, A. Nimbalker, K. Blankenship, B. Classon, T. Fuja, and D. Costello, “Contention-free interleavers,” Proc. Int. Symp. on Info. Theory, 2004.