CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci & Eng USF

Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 1, Gate-level combinational circuit

Recommended reading Wikipedia – The Free On-line Encyclopedia VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/Verilog

Brief History of VHDL

VHDL VHDL is a language for describing digital logic systems used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language 8

Genesis of VHDL State of art circa 1980 Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective: shortening the time from a design concept to implementation from 18 months to 6 months The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is the product of a US Government request for a new means of describing digital hardware. The Very High Speed Integrated Circuit (VHSIC) Program was an initiative of the Defense Department to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language. 9

A Brief History of VHDL July 1983: a DoD contract for the development of VHDL awarded to Intermetrics IBM Texas Instruments August 1985: VHDL Version 7.2 released December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard The contract for the first VHDL implementation was awarded to the team of Intermetrics, IBM, and Texas Instruments in July 1983. However, development of the language was not a closed process and was subjected to public review throughout the process (accounting for Versions 1 through 7.1). The final version of the language, developed under government contract, was released as VHDL Version 7.2. In March 1986, IEEE proposed a new standard VHDL to extend and modify the language to fix identified problems. In December 1987, VHDL became IEEE Standard 1076-1987. VHDL was again modified in September 1993 to further refine the language. These refinements both clarified and enhanced the language. The major changes included much improved file handling and a more consistent syntax and resulted in VHDL Standard 1076-1993. 10

Subsequent versions of VHDL IEEE-1076 1987 IEEE-1076 1993 ← most commonly supported by CAD tools IEEE-1076 2000 (minor changes) IEEE-1076 2002 (minor changes) IEEE-1076 2008

Verilog

Verilog Essentially identical in function to VHDL Simpler and syntactically different C-like Gateway Design Automation Co., 1985 Gateway acquired by Cadence in 1990 IEEE Standard 1364-1995 (Verilog-95) Early de facto standard for ASIC design Two subsequent versions Verilog 2001 (major extensions) ← dominant version used in industry Verilog 2005 (minor changes) Programming language interface to allow connection to non-Verilog code

VHDL vs. Verilog Government Developed Commercially Developed Ada based C based Strongly Type Cast Mildly Type Cast Case-insensitive Case-sensitive Difficult to learn Easier to Learn More Powerful Less Powerful

Good VHDL/Verilog Books

Features of VHDL/Verilog Technology/vendor independent Portable Reusable

VHDL Fundamentals

Naming and Labeling (1) VHDL is case insensitive. Example: Names or labels databus Databus DataBus DATABUS are all equivalent

Naming and Labeling (2) General rules of thumb (according to VHDL-87) All names should start with an alphabet character (a-z or A-Z) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.) Do not use two or more consecutive underscore characters (_ _) within a name (e.g., Sel_ _A is invalid) No forward slashes “/” in names. All names and labels in a given entity and architecture must be unique.

Should not be used to avoid confusioin! Extended Identifiers Allowed only in VHDL-93 and higher: Enclosed in backslashes May contain spaces and consecutive underscores May contain punctuation and reserved characters within a name (!, ?, ., &, +, -, etc.) VHDL keywords allowed Case sensitive Examples: \rdy\ \My design\ \!a\ \RDY\ \my design\ \-a\ Should not be used to avoid confusioin!

Free Format VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space, tabs, and carriage return treated the same way. Example: if (a=b) then or if (a=b) then if (a = b) then are all equivalent

Readability standards & coding style Adopt readability standards based on the textbook by Chu Use coding style recommended in OpenCores Coding Guidelines Available at the course web page Penalty may be enforced for not following these recommendations!!!

Comments Comments in VHDL are indicated with a “double dash”, i.e., “--” Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over a couple of lines Examples: -- main subcircuit Data_in <= Data_bus; -- reading data from the input FIFO

Comments Explain function of module to other designers Explanatory, not Just restatement of code Placed close to the code described Put near executable code, not just in a header

Design Entity

Example: NAND Gate a b z 1 a z b

Example VHDL Code 3 sections of VHDL code to describe a design. File extension for a VHDL file is .vhd Name of the file should be the same as the entity name (nand_gate.vhd) [OpenCores Coding Guidelines] LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE model OF nand_gate IS BEGIN z <= a NAND b; END model; LIBRARY DECLARATION ENTITY DECLARATION ARCHITECTURE BODY

Design Entity Design Entity - most basic building block of a design. entity declaration architecture 1 architecture 2 architecture 3 design entity Design Entity - most basic building block of a design. One entity can have many different architectures.

Entity Declaration Entity Declaration describes an interface of the component, i.e. input and output ports. Entity name Port names Semicolon Port type ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); END nand_gate; No Semicolon after last port Port modes (data flow directions)

Entity declaration – simplified syntax ENTITY entity_name IS PORT ( port_name : port_mode signal_type; …………. port_name : port_mode signal_type ); END entity_name;

Port Mode IN Entity Port signal a Driver resides outside the entity

Port Mode OUT c <= z Driver resides inside the entity Entity Port signal z Output cannot be read within the entity c c <= z

Port Mode OUT (with extra signal) Driver resides inside the entity Entity Port signal x z Signal x can be read inside the entity c z <= x c <= x

Port Mode INOUT Entity Port signal a Signal can be read inside the entity Driver may reside both inside and outside of the entity

Port Modes - Summary The Port Mode of the interface describes the direction in which data travels with respect to the component In: Data comes into this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment. Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

Architecture (Architecture body) Describes an implementation of a design entity Architecture example: ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; Logic operators: NOT, AND, OR, NAND, NOR, XOR, XNOR

Architecture – Simplified Syntax ARCHITECTURE architecture_name OF entity_name IS Declarations BEGIN Concurrent statements END architecture_name;

Entity Declaration & Architecture LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow;

Tips & Hints Place each entity in a different file. The name of each file should be exactly the same as the name of an entity it contains. These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs

Tips & Hints Place the declaration of each port, signal, constant, and variable in a separate line for better readability These rules are not enforced by all tools but are worth following in order to increase readability and portability of your designs

Libraries

Library Declarations LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow; Library declaration Use all definitions from the package std_logic_1164

Library Declarations - Syntax LIBRARY library_name; USE library_name.package_name.package_parts;

Structure of a Library LIBRARY PACKAGE 1 PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS

Libraries ieee std work Specifies digital logic system, including STD_LOGIC, and STD_LOGIC_VECTOR types Need to be explicitly declared Specifies built-in data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc. Visible by default Holds current designs after compilation

STD_LOGIC Demystified

STD_LOGIC LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand_gate IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); END nand_gate; ARCHITECTURE dataflow OF nand_gate IS BEGIN z <= a NAND b; END dataflow;

BIT versus STD_LOGIC BIT type can only have a value of ‘0’ or ‘1’ STD_LOGIC can have nine values ’U’,’X’,‘0’,’1’,’Z’,’W’,’L’,’H’,’-’ Useful mainly for simulation ‘0’,’1’, and ‘Z’ are synthesizable (your codes should contain only these three values)

STD_LOGIC type demystified Value Meaning ‘U’ Uninitialized ‘X’ Forcing (Strong driven) Unknown ‘0’ Forcing (Strong driven) 0 ‘1’ Forcing (Strong driven) 1 ‘Z’ High Impedance ‘W’ Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’ Don't Care Signals are used to connect different parts of a design. They can be thought of as “wire” in conventional sense. Every signal has a type. A type is all the valid values that a signal can assume. VHDL naturally supports bit type, which allows signals of this (bit) type to take the values ‘0’ or ‘1’. Signals of type integer can take integer values between +(231 – 1) to -(231-1). Wire in real implementation may need to take an unknown value, ‘X’ or high impedance value, ‘Z’. Thus, IEEE 1164 standard defined std_logic with nine values listed in Table 1. Std_logic_vector is an array or vector of std_logic type. It represents a bus and has dimension associated with it, which is known as the range of vector.

More on STD_LOGIC Meanings (1) ‘1’ ‘X’ Contention on the bus ‘0’

More on STD_LOGIC Meanings (2)

Resolving logic levels U X 0 1 Z W L H - U U U U U U U U U U X U X X X X X X X X 0 U X 0 X 0 0 0 0 X 1 U X X 1 1 1 1 1 X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 1 L W L W X H U X 0 1 H W W H X - U X X X X X X X X

STD_LOGIC Rules In this course, use only std_logic or std_logic_vector for all entity input or output ports Do not use integer, unsigned, signed, bit for ports You can use them inside of architectures if desired You can use them in generics Instead use std_logic_vector and a conversion function inside of your architecture [Consistent with OpenCores Coding Guidelines]

Modeling Wires and Buses

Signals a b SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); a wire 1 b bus 8

Standard Logic Vectors SIGNAL a: STD_LOGIC; SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0); ………. a <= ‘1’; -- assign ‘a’ with logic ONE b <= ”0000”; -- Binary base assumed by default c <= B”0000”; -- Binary base explicitly specified d <= X”AF67”; -- Hexadecimal base e <= O”723”; -- Octal base

Vectors and Concatenation SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111” d <= ‘0’ & ”0001111”; -- d <= ”00001111” e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- e <= ”00001111”

Types of VHDL Description (Modeling Styles)

Types of VHDL Descriptions Testbenches dataflow structural behavioral Concurrent statements Components and interconnects Sequential statements Registers State machines Decoders Subset most suitable for synthesis

Types of VHDL Descriptions: Alternative View Behavioral Structural dataflow algorithmic Components & interconnects Concurrent statements Sequential statements

xor3 Example

Entity xor3_gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor3 IS PORT( A : IN STD_LOGIC; B : IN STD_LOGIC; C : IN STD_LOGIC; Result : OUT STD_LOGIC ); end xor3_gate;

Dataflow Architecture (xor3_gate) ARCHITECTURE dataflow OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1_OUT <= A XOR B; Result <= U1_OUT XOR C; END dataflow; U1_OUT

Dataflow Description Describe the same behavior Describes how data moves through the various processing steps of the system. Uses series of concurrent statements to realize logic. Most useful style when series of Boolean equations can represent a logic  used to implement simple combinational logic Dataflow code also called concurrent code Concurrent statements are evaluated at the same time; thus, the order of these statements does NOT matter This is not true for sequential/behavioral statements Describe the same behavior U1_out <= A XOR B; Result <= U1_out XOR C; Result <= U1_out XOR C; U1_out <= A XOR B;

Event-Driven Semantics When a concurrent statement is evaluated? An event is a change of value on a signal. Consider the example in the previous slide. when there is an event on a signal on the right hand side of an assignment. U1_out <= A XOR B; Result <= U1_out XOR C; Result <= U1_out XOR C; U1_out <= A XOR B;

Structural Architecture Body Result xor3 U1_OUT I1 I2 Y I1 I2 Y LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor2 IS PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC); END xor2; ARCHITECTURE dataflow OF xor2 IS BEGIN Y <= I1 xor I2; END dataflow; xor2.vhd

Structural Architecture in VHDL 93 B C Result xor3 U1_OUT I1 I2 Y I1 I2 Y ARCHITECTURE structural OF xor3_gate IS SIGNAL U1_OUT: STD_LOGIC; BEGIN U1: entity work.xor2(dataflow) PORT MAP ( I1 => A, I2 => B, Y => U1_OUT); U2: entity work.xor2(dataflow) PORT MAP ( I1 => U1_OUT, I2 => C, Y => Result); END structural;

Structural Architecture in VHDL 87 ARCHITECTURE structural OF xor3 IS SIGNAL U1_OUT: STD_LOGIC; COMPONENT xor2 PORT( I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END COMPONENT; BEGIN U1: xor2 PORT MAP (I1 => A, I2 => B, Y => U1_OUT); U2: xor2 PORT MAP (I1 => U1_OUT, I2 => C, Y => Result); END structural; A B C Result xor3 U1_OUT I1 I2 Y I1 I2 Y

Structural Description Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. Structural style is useful when expressing a design that is naturally composed of sub-blocks.

Behavioral Architecture (xor3 gate) ARCHITECTURE behavioral OF xor3 IS BEGIN xor3_behave: PROCESS (A, B, C) IF ((A XOR B XOR C) = '1') THEN Result <= '1'; ELSE Result <= '0'; END IF; END PROCESS xor3_behave; END behavioral;

Behavioral Description It describes what happens on the inputs and outputs of the black box (no matter how a design is actually implemented). Similar to dataflow style, More like sequential SW programming. This style uses PROCESS statements in VHDL. A process itself is a concurrent statement. A process consist of sequential statements.

Design Testing and Testbenches After a design is done, it needs to be tested. During testing, design inputs are driven by various test vectors, and Outputs are monitored and checked. Test vector generator UUT/ DUT Monitor

Testbench in VHDL library ieee; use ieee.std_logic_1164.all; Test vector generator UUT/ DUT Monitor Testbench library ieee; use ieee.std_logic_1164.all; ENTITY testbench IS END testbench;

ARCHITECTURE tb_arch OF testbench IS -- signal declarations BEGIN -- Instantiate the design under test. uut: entity work.xor3(structural) port map (A => A, … ); -- test vector generator process begin -- generate sequence of vectors to drive -- design inputs A, B, and C. end process; end tb_arch;

ARCHITECTURE tb_arch OF testbench IS -- signal declarations BEGIN … -- test vector generator process begin A <= ‘1’; -- first test vector B <= ‘0’; C <= ‘0’; wait for 20ns; -- wait for circuit to stablize end process; end tb_arch;

?