Renesas Electronics America Inc. © 2011 Renesas Electronics America Inc. All rights reserved. RX Direct Memory Access Controller (DMAC) Ver. 1.00

Course Introduction Purpose Provide details on the RX DMA Controller (DMAC) Content DMAC Overview Transfer Modes Register Set Overview DMAC Interrupts Learning Time 20 Minutes © 2011 Renesas Electronics America Inc. All rights reserved. 2

Direct Memory Access Controller (DMAC) © 2011 Renesas Electronics America Inc. All rights reserved. 3

DMAC Normal Transfer Mode One data per request (8/16/32-bit) DMSAR/DMDAR contain source & destination Increment/decrement/fixed/offset addition DMCRAL: Transfer counter, decremented each transfer Up to transfers (or free-running) Can generate interrupt at end of transfer (not in free-run) © 2011 Renesas Electronics America Inc. All rights reserved. 4 DMSARDMDAR Data 1 Data 2 Data 3 Data 4 Data 5 Transfer source data area Transfer destination data area Data 1 Data 2 Data 3 Data 4 Data 5

DMAC Repeat Transfer Mode One data per request (8/16/32-bit) DMSAR/DMDAR contain source & destination DMCRAH: Repeat area size (up to 1K) DMCRAL: Transfer count, decremented each transfer DMCRB: Block count, decremented after each repeat cycle Can generate interrupt at end of repeat or transfer © 2011 Renesas Electronics America Inc. All rights reserved. 5 DMSAR DMDAR Data 1 Data 2 Data 3 Data 4 Source areaDestination area Data 1 Data 2 Data 3 Data 4 Data 1 Data 2 Data 3 Data 4

DMAC Block Transfer Mode One block per request DMSAR/DMDAR contain source & destination (inc/dec/offset) DMCRAH: Block size (up to 1K) DMCRAL: Transfer count (copy of DMCRAH) DMCRB: Block count, decremented after each block xfer Can generate interrupt at end of block or transfer © 2011 Renesas Electronics America Inc. All rights reserved. 6 DMSAR DMDAR Source areaDestination area Block n First block Block Area

DMAC Registers Basic registers for all transfers Source & Destination Registers (DMSAR/DMDAR) Transfer Count Register (DMCRA) Block Counter Register (DMCRB) Mode & control registers Interrupt & status registers Registers from other RX subsystems Interrupt Control Unit (ICU) registers Peripheral registers © 2011 Renesas Electronics America Inc. All rights reserved. 7

DMAC Register Set © 2011 Renesas Electronics America Inc. All rights reserved. 8 SymbolRegister nameAccess sizeFunction DMSARDMA source address register32Address DMDARDMA destination address register32Address DMCRADMA transfer count register32Count DMCRBDMA block transfer count register16Count DMTMDDMA transfer mode register16Mode DMINTDMA interrupt setting register8Interrupt DMAMDDMA address mode register16Address DMOFR 1 DMA offset register32Address DMCNTDMA transfer enable register8Control/status DMREQDMA software start register8Control/status DMSTSDMA status register8Control/status DMCSLDMA activation source flag control register8Interrupt DMAST 2 DMA start register8Control/status Notes 1 Only on channel DMAC0 2 One register common to all channels

DMAC Source & Destination Address Registers 32-bit Source & Destination Addresses for Transfers Valid ranges (256 Mbytes each): 0x to 0x0FFF FFFF, 0xF to 0xFFFF FFFF DMAC Address Mode Register controls inc/dec/offset © 2011 Renesas Electronics America Inc. All rights reserved. 9 DMA Source Address Register (DMSAR) b31b16 b0b15 DMA Destination Address Register (DMDAR) b31b16 b0b15

DMAC Transfer Count Register (DMCRA) Normal mode: DMCRAL contains 16-bit counter Repeat & block xfer mode: DMCRAH contains repeat or block size DMCRAL contains repeat or block count (init to DMCRAH) © 2011 Renesas Electronics America Inc. All rights reserved. 10 Normal transfer mode: b31b16 b0b15 16-bit transfer counter b25b26 Repeat transfer mode; block transfer mode b31b16 b0b15 b25b26 Repeat/block size Repeat/block count b9

DMAC Block Transfer Count Register (DMCRB) Normal mode: Not used Repeat & block xfer mode: Number of repeat/block transfers 0x001 to 0x3FF (1 to 1023) 0x000 (1024) © 2011 Renesas Electronics America Inc. All rights reserved. 11 Repeat transfer mode; block transfer mode b15b0b9b10 # of repeats/blocks

DMAC Interrupts Interrupts to start DMAC transfer ICU: DMACA Activation Source Select Registers (DMRSR0-3) Install the vector number of the interrupt source Not all sources can trigger DMAC Interrupts generated by DMAC At each transfer At each repeat/block completion At end of all transfers Controlled by DMINT register © 2011 Renesas Electronics America Inc. All rights reserved. 12 b0 DMRS[7:0] b7 DMRSRn (n=0-3)

Summary DMAC Overview Transfer Modes Normal Repeat Transfer Register Set DMAC Interrupts Into DMAC to start transfers Out of DMAC to indicate status Thank you! © 2011 Renesas Electronics America Inc. All rights reserved. 13

Renesas Electronics America Inc. Thank You © 2011 Renesas Electronics America Inc. All rights reserved.