Sharif University of Technology Department of Computer Engineering Verilog ® HDL Basic Concepts Alireza Ejlali.

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Presentation transcript:

Sharif University of Technology Department of Computer Engineering Verilog ® HDL Basic Concepts Alireza Ejlali

Net Data Types (wire) Nets represent physical connections between structural entities. Nets represent physical connections between structural entities. A net value shall be determined by the values of its drivers. A net value shall be determined by the values of its drivers. A net may have 0,1,2 or more drivers. A net may have 0,1,2 or more drivers. If no driver is connected to a net, its value shall be high-impedance (z). If no driver is connected to a net, its value shall be high-impedance (z).

Example1: a net with two drivers module example; reg i1,i2,i3,i4; reg i1,i2,i3,i4; wire o; wire o; and g1(o,i1,i2); and g1(o,i1,i2); or g2(o,i3,i4); or g2(o,i3,i4); initial initial begin begin i1=0; i2=0; i3=0; i4=0; i1=0; i2=0; i3=0; i4=0; #4 i1=1; i3=1; #4 i1=1; i3=1; #4 i2=1; i4=1; #4 i2=1; i4=1; #4 i1=0; i3=1; #4 i1=0; i3=1; #4 i2=0; i4=1; #4 i2=0; i4=1; end endendmodule

Register Data Types (reg) Registers are data storage elements (like variables in programming languages). Registers are data storage elements (like variables in programming languages). A register shall store a value from one assignment to the next. A register shall store a value from one assignment to the next. The default initialization value for a reg data type shall be the unknown value, x. The default initialization value for a reg data type shall be the unknown value, x.

Example2: Illegal reference to nets module example; reg i1,i2,i3,i4; reg i1,i2,i3,i4; wire o; wire o; and g1(o,i1,i2); and g1(o,i1,i2); or g2(o,i3,i4); or g2(o,i3,i4); initial initial begin begin i1=0; i2=0; o=0; //Illegal reference to net: o i1=0; i2=0; o=0; //Illegal reference to net: o i3=0; i4=0; i3=0; i4=0; #4 i1=1; i3=1; #4 i1=1; i3=1; #4 i2=1; i4=1; #4 i2=1; i4=1; #4 i1=0; i3=1; #4 i1=0; i3=1; #4 i2=0; i4=1; #4 i2=0; i4=1; end endendmodule

Assignment 1 Design a 4-bit binary adder using top-down methodology. Design a 4-bit binary adder using top-down methodology. Write a behavioral description for HA units. Write a behavioral description for HA units. Delay (S)= 5, Delay (C)=2 Delay (S)= 5, Delay (C)=2 Use structural description for all the other parts. Use structural description for all the other parts. Write a testbench for your design. Write a testbench for your design. What is the delay of the 4-bit binary adder (use ModelSim). What is the delay of the 4-bit binary adder (use ModelSim).

Integer Keyword: integer Keyword: integer integer variables are signed numbers integer variables are signed numbers Bit width: implementation-dependent (at least 32- bits) Bit width: implementation-dependent (at least 32- bits) Designer can also specify a width: Designer can also specify a width: integer [7:0] tmp; integer [7:0] tmp; Examples: Examples: integer counter; initial counter = -1; counter = -1;

Real Keyword: real Keyword: real Values: Values: Default value: 0 Default value: 0 Decimal notation: Decimal notation: Scientific notation: 3e6 (=3x10 6 ) Scientific notation: 3e6 (=3x10 6 ) Cannot have range declaration Cannot have range declaration Example: Example: real delta; initialbegin delta=4e10; delta=4e10; delta=2.13; delta=2.13;end integer i; initial i = delta; // i gets the value 2 (rounded value of 2.13) i = delta; // i gets the value 2 (rounded value of 2.13)

Time Used to store values of simulation time Used to store values of simulation time Keyword: time Keyword: time Bit width: implementation-dependent (at least 64) Bit width: implementation-dependent (at least 64) $time system function gives current simulation time $time system function gives current simulation time Example: Example: time save_sim_time; initial save_sim_time = $time; save_sim_time = $time;

Arrays Only one-dimensional arrays supported Only one-dimensional arrays supported Allowed for reg, integer, time Allowed for reg, integer, time Not allowed for real data type Not allowed for real data type Syntax: Syntax: [start_idx : end_idx]; [start_idx : end_idx]; Examples: Examples: integer count[0:7]; reg bool[31:0]; time chk_point[1:100]; reg [4:0] port_id[0:7]; integer matrix[4:0][4:0]; // illegal count[5]chk_point[100]port_id[3] Note the difference between vectors and arrays Note the difference between vectors and arrays