Digital Electronics Tutorial: Number System & Arithmetic Circuits Solutions

Number System  Conversion to Base 10  FFA 16     Binary Addition in 2’complement      Binary Subtraction in 2’complement    

Number System Solutions (1/3)  Conversion to Base 10  FFA 16 = F × F × A × 16 0 = 15 × × × 16 0 = 4090  = 1 × × × × × × × 2 0 = 108  = 1 × × × × 2 0 = 8  = 1 × × × × 16 0 = 4096

Number System Solutions (2/3)  Binary Addition in 2’complement __________ __________ __________ Overflow __________ Overflow

Number System Solution (3/3)  Binary Subtraction in 2’complement  =  =  =  = Overflow Overflow

Arithmetic Circuits Implement a combinational logic circuit that converts a 4-bit sign and magnitude numbers into corresponding 4-bit two’s complement numbers. Draw an input/output conversion truth table, intermediate K-maps, and your minimised two-level logic description.

Arithmetic Circuits Solution (1/4) ABCDEFGH CD AB E = AB + AC + AD

Arithmetic Circuits Solution (2/4) ABCDEFGH CD AB F = A ’ B + B C’ D’ + A B’ D + A B’ C

Arithmetic Circuits Solution (3/4) ABCDEFGH CD AB G = C D ’ + A’ C + A C’ D

Arithmetic Circuits Solution (4/4) ABCDEFGH CD AB H = D

Bit-Serial Adder The traditional binary adder operates on all of its input bits at the same time, calculating the sum output bits in parallel. Consider an alternative way to implement a binary adder using a so-called bit serial approach. The two numbers to be added are presented to a Finite State Machine one bit at a time, with the lowest order bits presented first. The Finite State Machine produces at its output the lowest order bit of the sum, then the next higher order sum bit, and so on, until all of the input bits have been processed and all of the output sum bits generated. (a) Design a simple datapath for the bit-serial adder down to the gate level, and identify the interface between your control finite state machine and the datapath. Consider how to deal with carry-in and carry-out in your design. (b) Show your state diagram for a 4-bit bit-serial adder, where the outputs of the state machine are the control signals of the datapath you designed in (a). (c) Demonstrate how your subsystem works by showing step-by-step how it executes the summation of 0110 and The carry-in to the low order bit is initially zero.

Bit-Serial Adder Solution (1/3) (a) Design a simple datapath for the bit- serial adder down to the gate level, and identify the interface between your control finite state machine and the datapath. Consider how to deal with carry-in and carry-out in your design. Signals: SHIFT, CinSELECT, SELECT, CE

Bit-Serial Adder Solution (2/3) (b) Show your state diagram for a 4-bit bit-serial adder, where the outputs of the state machine are the control signals of the datapath you designed in (a).

Bit-Serial Adder Solution (3/3) (c) Demonstrate how your subsystem works by showing step-by-step how it executes the summation of 0110 and The carry-in to the low order bit is initially zero. A[3:0] = 0110B[3:0] = 1100Cin = = A[3:0] = 0110B[3:0] = 1100 Step 1:SELECT = 00CinSELECT = 0SUM = 0000Cout = 0 Step 2:SELECT = 01CinSELECT = 1SUM = 1000Cout = 0 Step 3:SELECT = 10CinSELECT = 1SUM = 0100Cout = 1 Step 4: SELECT = 11CinSELECT = 1SUM = 0010Cout = 1 Cout Sum