Arvutitehnika instituut ati.ttu.ee Department of Computer Engineering ati.ttu.ee.

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Presentation transcript:

Arvutitehnika instituut ati.ttu.ee Department of Computer Engineering ati.ttu.ee

Department of Computer Engineering 2 Abstraction Levels ArchitectureStructureLogic Algorithm Programming Integrated Circuit Device AB A+B

Department of Computer Engineering 3 What is Technology Scaling Drawn to the same scale 1.0 μm Mid 1980s Speed: 10 MHz 0.1 μm Early 2000’s Speed: 3 GHz Today: 65 nm, going down to 22 nm by nm MOS Transistor50nm

Department of Computer Engineering 4 Power Density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

Department of Computer Engineering 5 Execution core 120 o C Cache Temp ( o C) Thermal map: 1.5 GHz Itanium-2 [Source: Intel Corporation and Prof. V. Oklobdzija]

Department of Computer Engineering 6 The Result

Department of Computer Engineering 7 Our main competences Hardware and Software Systems-on-Chip (SoC), Networks-on-Chip (NoC), Systems-in-a-Cube (SiC) HW/SW Co-design Fault tolerance, diagnosis, test Web applications SW quality

Department of Computer Engineering 8 HW Synthesis FPGA-based development kits (Xilinx)

Department of Computer Engineering 9 SoC, NoC and SiC Our activities: Modelling Design Analysis Optimization Access to the CAD software from the leading vendors: Synopsys, Mentor Graphics, Cadence, etc. Intel 8x10 NoC

Department of Computer Engineering 10 © IBM Testing Manufacturing defects Contamination (dust) Misalignment Impurity... O&M defects Aging Particles...

Department of Computer Engineering 11 Testing Equiopment from Göpel and Saab Stimul. Response Yes, No  Diagnosis Yes, No  Diagnosis

Department of Computer Engineering 12 USBUSB USER SERVER INTERNET USER Defect Investigation Environment

Department of Computer Engineering 13 Overview of Remote Laboratory DefSim - an integrated measurement environment for physical defect study in CMOS circuits. TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability Web-based runtime interface for remote access to our tools Java applets – illustrative e-learning software written specifically for the web

Department of Computer Engineering 14 Used in 100+ institutions in 40+ countries Design Error Diagnosis Test Generators BIST Emulator Design Test Set Levels: Gate Macro RTL Fault Table Test Set Optimizer Methods: BILBO CSTP Hybrid Faulty Area Circuits: Combinational Sequential Logic Simulator Formats: EDIF AGM Defect Library Hazard Analysis Data Specifi- cation Algorithms: Deterministic Random Genetic Multivalued Simulator Fault models: Stuck-at faults Physical defects Fault Simulator PC-Based Toolkit – Turbo Tester

Department of Computer Engineering 15 E-Learning Software Logic level diagnostics System level test & DfT Software for classroom, home, labs and exams: Boundary Scan

Department of Computer Engineering 16 BIST Analyzer