Modulo-N Counters According to how they handle input transitions –Synchronous –Asynchronous

General Modulo-N asynchronous Counter Number of flip-flops? Number of states? Why the name “Modulo” Which state does the logic detect?

Asynchronous BCD counter –Which is the last stable output?

Asynchronous BCD counter State diagram –Counter passes through intermediate transient states (small circles) between the steady states (the large circles) Which is the last unstable output and why?

Constructing asynchronous Modulo-N counters from binary Asynchronously resetting modulo-13 counter What are the problems with asynchronous design?

Synchronous Modulo-13 counter Which state should the reset logic of a synchronous Modulo-N counter sense?

Shift registers as counters Number of storage elements (FFs)? Number of states? Bit patterns? Where is a ring counter useful?

Ring counter Schematic Transition diagram

Ring counter equivalent Can use a small counter plus a decoder Why?

Is the clear synchronous or asynchronous? What is the drawback of this circuit? Ring counter equivalent

Twisted Ring counter AKA Johnson Counter How does it work? Number of unique states? State sequence? Advantages over ring counter?

Twisted Ring counter Number of unique states? –2n (n is # of flip- flops) Advantages over ring counter? –Half the number of flip-flops

Twisted Ring counter example

Desired timing diagram Using ring counter – 2n states = 16; n =8 Choose 8-bit shift register SN74164 and an inverter for the twist Figure out the decoding logic for the functions

Twisted Ring counter example

Logic diagram of the circuit

Twisted Ring counter example Timing diagram of the circuit

Alternative implementations 1) Using a ring counter 2) Using a straight binary counter What are advantages and disadvantages of each? –Twisted vs. non-twisted: Half the Flip-Flops Decode logic –Straight binary vs. ring Exponentially fewer flip-flops for the straight counter More logic

Fractional rate multiplier –Clock drives an n-bit binary counter with outputs X 1 …X n –Produce non-overlap pulse trains P 1 …P n

Fractional rate multiplier –The separation between the output pulses obtained by the fractional multiplier will vary –They are synchronized with the input clock

Fractional rate multiplier Why don’t P i overlap? –What is the product P i P j ? How many pulses does each P i generate per 2 n clocks? –X1 is on ½ of the time –X2 is on ¼ of the time