More Intro MIPS Computer Organization I 1 September 2009 © McQuain, Feng & Ribbens Machine Language But, how is all of this driven? Machine language: -registers store collections of bits -all data and instructions must be encoded as collections of bits (binary) -bits are represented as electrical charges (more or less) -control logic and arithmetic operations are implemented as circuits, which are driven by the movement of electrical charges -so, the instructions directly manipulate the underlying hardware (cool, huh?) The collection of all valid binary instructions is known as the machine language. -what’s valid depends on the design of the hardware, especially the control circuitry -must be formally specified -machine language is not human-friendly

More Intro MIPS Computer Organization I 2 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens Simple instructions, all 32 bits wide Very structured, no unnecessary baggage Only three instruction formats: Overview of MIPS Machine Language Basic arithmetical-logical instructions are R-format. Load/store/conditional branch instructions are I-format. Jump/unconditional branch instructions are J-format. R functshamtrdrtrsop 16-bit immediatertrsop 26-bit immediateop I J

More Intro MIPS Computer Organization I 3 September 2009 © McQuain, Feng & Ribbens MIPS Machine Language: Arithmetic Machine language basic arithmetic/logic instruction format: functshamtrdrtrsop Can you guess what the field names stand for? opoperation code (opcode) rs1 st source register rt2 nd source register rddestination register shamtshift amount functopcode variant selector

More Intro MIPS Computer Organization I 4 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens What will be involved in executing a machine language instruction? Consider an I-type instruction, say a lw (load word) instruction: Anticipating Execution 16-bit immediatertrsop I The opcode bits must be analyzed to determine that the instruction is lw. The contents of $rs must be fetched to the ALU and added to the immediate field to compute the appropriate address. The contents at that address must be fetched from memory and written to register $rt.

More Intro MIPS Computer Organization I 5 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens Decoding the Opcode We will need some sort of control logic that takes the 6-bit opcode and determines what specific machine instruction it corresponds to, and then triggers the necessary operations of other hardware units. The control logic will be purely combinational. Each hardware component, like the ALU will take certain control inputs; it will be the job of the decoder unit to set those control lines. Note: for R-type instructions, this will be a little more involved.

More Intro MIPS Computer Organization I 6 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens The registers must be organized in some way that makes it possible to conduct a transaction of the form "give me the contents of register number K". Such a device is called a register file. A register file has an input port that accepts a register number (a 5-bit port in our case) from which data will be read. The register file processes that input and channels the contents of the corresponding register to an output port (a 32-bit port in our case). Fetching Register Operands

More Intro MIPS Computer Organization I 7 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens The value fetched from the register must be combined with the 16-bit immediate value from the instruction. This will require an adder circuit, but we will embed that in a more complex arithmetic- logic unit (ALU). The ALU will accept two 32-bit values (operands) and accept control input bits that specify which operation is to be applied to those operands. The ALU will supply the computed result to a 32-bit output port. Note: the ALU will be designed to take 32-bit operands. That means that the 16-bit value taken from the instruction must be widened to 32-bits, and that must be done in such a way that the sign of the immediate value is preserved. Computing the Address

More Intro MIPS Computer Organization I 8 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens There must be a memory unit that has an input port that will accept a 32-bit address. The memory unit must have a control input that specifies a value is to be read from that address (as opposed to being written to it). The memory unit must have a 32-bit output port to which the memory unit can channel the requested data value. Fetching the Data

More Intro MIPS Computer Organization I 9 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens The register file must have an input port that accepts a register number to which data will be written. It will also need a control input to trigger the write operation. Loading the Data to a Register

More Intro MIPS Computer Organization I 10 September 2009 © McQuain, Feng & Ribbens ©2009 McQuain & Ribbens A careful examination of the previous few slides will also reveal the need for a number of connections to channel data from one hardware component to another. For example, there must be a way to move data from the register file's output port to the ALU's input ports. In order to design a datapath for executing MIPS machine language instructions, we must identify all the hardware components we will need, and the necessary connections, and the necessary control logic and control lines… Connections

More Intro MIPS Computer Organization I 11 September 2009 © McQuain, Feng & Ribbens CPU Overview

More Intro MIPS Computer Organization I 12 September 2009 © McQuain, Feng & Ribbens MIPS Registers Registers bit general-purpose registers, referred to as $0, $1, …, $ bit floating-point registers, referred to as $f0, $f1, … $f bit floating-point registers, referred to as $f0, $f2, … $f30 -conventions govern the use of the general registers We will, for now, adopt the view that the underlying computer is a “black box” that understands MIPS machine language.

More Intro MIPS Computer Organization I 13 September 2009 © McQuain, Feng & Ribbens Registers vs. Memory Operands to arithmetic and logical instructions must be registers or immediates. Compiler associates variables with registers What about programs with lots of variables? ProcessorI/O Control Datapath Memory Input Output

More Intro MIPS Computer Organization I 14 September 2009 © McQuain, Feng & Ribbens Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory bits of data

More Intro MIPS Computer Organization I 15 September 2009 © McQuain, Feng & Ribbens MIPS Memory Organization Bytes are nice, but most data items use larger "words" For MIPS, a word is 32 bits or 4 bytes bits of data Registers hold 32 bits of data 2 32 bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned, that is, each has an address that is a multiple of 4. MIPS can be either big-endian (that is, the address of each word is the address of the “left-most” byte of the word) or little-endian. This is important when viewing the contents of memory.

More Intro MIPS Computer Organization I 16 September 2009 © McQuain, Feng & Ribbens CPU Overview