1 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 21: Fri 11/4/2011 (System Architectures) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) MP3: Due 11/4 –Make sure when done with hardware Close minicom Close xmd cleanly Also run “ps aux | grep xmd” to check that xmd has exited if not then use “kill -9” to kill the process. Not doing these is locking up the download cables preventing others from testing. Weekly Project Updates due: Friday’s (midnight) Announcements/Reminders

3 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –20% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

4 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Teams Formed and Topic: Mon 10/10 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/14 –Power Point 5-10 slides (presentation to class Wed 10/19) System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

6 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Work on projects: 10/ /9 –Weekly update reports More information on updates will be given Presentations: Finals week –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

7 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

8 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

9 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Common Questions

10 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Common Questions

11 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Common System Architectures Plus/Delta feedback Overview

12 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Introduction to common System Architectures What you should learn

13 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Design patterns (previous lecture) –Why are they useful? –Examples Compute models (Abstraction) –Why are they useful? –Examples System Architectures (Implementation) –Why are they useful? –Examples Outline

14 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Design patterns (previous lecture) –Why are they useful? –Examples Compute models (Abstraction) –Why are they useful? –Examples System Architectures (Implementation) –Why are they useful? –Examples Outline

15 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) References Reconfigurable Computing (2008) [1] –Chapter 5: Compute Models and System Architectures Scott Hauck, Andre DeHon

16 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Compute Models: Help express the parallelism of an application System Architecture: How to organize application implementation System Architectures

17 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Compute model and system architecture should work together Both are a function of –The nature of the application Required resources Required performance –The nature of the target platform Resources available Efficient Application Implementation

18 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA)

19 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Compute Model System Architecture

20 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Compute Model System Architecture

21 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Data Flow Compute Model System Architecture Streaming Data Flow

22 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Data Flow Compute Model System Architecture Streaming Data Flow

23 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Compute Model System Architecture

24 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Compute Model System Architecture Data Parallel Vector

25 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Data Flow Compute Model System Architecture Streaming Data Flow

26 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Data Flow Compute Model System Architecture Streaming Data Flow

27 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Efficient Application Implementation Application (Image Processing) Platform 1 (Vector Processor) Platform 2 (FPGA) Data Flow Compute Model System Architecture Streaming Data Flow XX +

28 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data presence – variable length connections between operators – data rates vary between operator implementations –data rates varying between operators Datapath sharing –not enough spatial resources to host entire graph –balanced use of resources (e.g. operators) –cyclic dependencies impacting efficiency Interconnect sharing –Interconnects are becoming difficult to route –Links between operators infrequently used –High variability in operator data rates Streaming coprocessor –Extreme resource constraints Implementing Streaming Dataflow

29 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX +

30 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX + data_ready

31 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX + data_ready FIFO data_ready

32 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX + data_ready FIFO data_ready stall

33 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX + data_ready FIFO data_ready stall Flow control: Term typical used in networking

34 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data Presence XX + data_ready FIFO data_ready stall Flow control: Term typical used in networking Increase flexibility of how application can be implemented

35 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data presence – variable length connections between operators – data rates vary between operator implementations –data rates varying between operators Datapath sharing –not enough spatial resources to host entire graph –balanced use of resources (e.g. operators) –cyclic dependencies impacting efficiency Interconnect sharing –Interconnects are becoming difficult to route –Links between operators infrequently used –High variability in operator data rates Streaming coprocessor –Extreme resource constraints Implementing Streaming Dataflow

36 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing XX +

37 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing XX + Platform may only have one multiplier

38 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing X + Platform may only have one multiplier

39 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing X + Platform may only have one multiplier REG

40 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing X + Platform may only have one multiplier REG FSM

41 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Datapath Sharing X + Platform may only have one multiplier REG FSM Important to keep track of were data is coming!!

42 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data presence – variable length connections between operators – data rates vary between operator implementations –data rates varying between operators Datapath sharing –not enough spatial resources to host entire graph –balanced use of resources (e.g. operators) –cyclic dependencies impacting efficiency Interconnect sharing –Interconnects are becoming difficult to route –Links between operators infrequently used –High variability in operator data rates Streaming coprocessor –Extreme resource constraints Implementing Streaming Dataflow

43 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Interconnect sharing XX +

44 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Interconnect sharing XX + Need more efficient use of interconnect

45 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Interconnect sharing XX + Need more efficient use of interconnect

46 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Interconnect sharing XX + Need more efficient use of interconnect FSM

47 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Data presence – variable length connections between operators – data rates vary between operator implementations –data rates varying between operators Datapath sharing –not enough spatial resources to host entire graph –balanced use of resources (e.g. operators) –cyclic dependencies impacting efficiency Interconnect sharing –Interconnects are becoming difficult to route –Links between operators infrequently used –High variability in operator data rates Streaming coprocessor –Extreme resource constraints Implementing Streaming Dataflow

48 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) See SCORE chapter 9 of text for an example. Streaming coprocessor

49 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Typically thought of in the context of sequential programming on a processor (e.g. C, Java programming) Key to organizing synchronizing and control over highly parallel operations –Time multiplexing resources: when task to too large for computing fabric –Increasing data path utilization Sequential Control

50 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Sequential Control X XX + + AX BC

51 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Sequential Control X XX + + AX BC A*x 2 + B*x + C

52 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Sequential Control X XX + + AX BC A*x 2 + B*x + C X + A X B C

53 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Finite State Machine with Datapath (FSMD) A*x 2 + B*x + C X + A X B C

54 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Finite State Machine with Datapath (FSMD) A*x 2 + B*x + C X + A X B C FSM

55 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Finite State Machine with Datapath (FSMD) Very Long Instruction Word (VLIW) data path control Processor Instruction augmentation Phased reconfiguration manager Worker farm Sequential Control: Types

56 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Single Program Multiple Data Single Instruction Multiple Data (SIMD) Vector Vector Coprocessor Data Parallel

57 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Cellular Automata

58 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Next Lecture

59 - CPRE 583 (Reconfigurable Computing): System Architectures Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR