CHEF 2013 – 22-25th April 2013 – Paris LHCb Calorimeter Upgrade Electronics E. Picatoste (Universitat de Barcelona) On behalf of the LHCb group

24 th April 2013CHEF LHCb Upgrade OT VELO RICH-1 TT IT Magnet Muon Stations M2-M5 -5m 5m y 10m0m Calorimeters RICH-2 M1 Statistical improvement if: Increase of data rate from 1 to 5fb -1 /year Increase luminosity to 2x10 33 cm -2 s -1 Increase trigger efficiencies Current L0 trigger limited by electronics ⇒ upgrade: Trigger in software Use data from every bunch crossing Upgrade electronics and DAQ Scheduled for the long LHC shutdown in m15m More details on “LHCb Calorimeter upgrade”: talk of Yu. Guz, this conference

3 Upgrade Architecture 24 th April 2013CHEF 2013 Ken Wyllie, CERN3 HLT Current HLT++ Upgrade 1MHz event rate 40MHz event rate Readout Supervisor L0 Hardware Trigger Readout Supervisor Low-Level Trigger 50 Tb/s Low-Level Trigger More details on “LHCb Calorimeter upgrade”: talk of Yu. Guz, this conference 1 to 40 MHz LOW Level Trigger decision from Front-End to Back-End

FEB CBTVB 4 Current Front-End Electronics 24 th April 2013CHEF 2013 Front End Board FePGA (ACTEL AX250) Analog EE (4 Ch) ASIC GluePGA (Actel APA150) 1.2 GHz link for data 4 channels Pedestal subtraction Gain correction Buffer triggered by L0 Detector cells PMT clip 12m … 16 FEB in 1 CRATE 32 ch … On gantry over detector CRATE Slow control interface Spying data SecPGA (Actel APA300) Data readout Serialize data TrigPGA (Actel AX500) Trigger info E T in cluster Neighbours Crate and Readout Controller Board Slow control Fast control Detector clock Optical link to DAQ Trigger Validation Board … … 8xFePGA Crate and Readout Controller Board Trigger Validation Board Trigger info from FEBs to L1 trigger 1.2 GHz link to trigger validation crate 8xanalog blocks

FEB CB 5 Upgrade Front-End Electronics 24 th April 2013CHEF 2013 CRATE Front End Board Clk manager Clk[7:0] In Ref Down- link Uplink General Ctrl GBTX E-Port ACTEL FPGA (A3PE1500): reprogrammable rad tolerant up to 15-20krad LVS-SLVS translator Giga Bit Transceiver (GBT): 1xTRIGGER + 4xDATA Analog EE (8 Ch) E-Port SCA Network Controller User Buses : {I2C, //, SPI, JTAG, 12bADC, …} Translator SLVS-LVDS FPGA, Buffer, … 4 link per FEB for data 1 link per FEB for LLT Functions: Pedestal subtraction Data packing and formatting Compute trigger info (BXID, Calo hit #, EE address,…) Detector cells PMT clip 12m … Slow control from Control Board through Backplane Clock from Control Board through backplane 16 FEB in 1 CRATE Control Board GBTX SCA CLOCK distribution to FEB through backplane Slow control to FEB through Backplane 32 ch … On gantry over detector Rad dose: ~1krad/year 40MSPS 40MSPS 4xanalog blocks

Clipping: ⇒ Reduce signal tail ⇒ Reduce spill over Front End Board 12b ADC Detector cells clip 12m cable -+-+ PMT 5ns 50Ω 50Ω 25ns 100Ω 100Ω BUFFER R f = 12MΩ C f = 4pF 100nF 22nF INTEGRATOR Analog Chip 6 Current Analog Signal Processing Specifications: Pulse shaping in 25ns Spill over < 1% after 25ns Integrator plateau: 4ns Linearity < 1% Rise time ~ 5 ns 24 th April 2013CHEF 2013 Integrator discharge: Clipped signal + delayed negative clipped signal After clip Before clip BiCMOS 0.8um integrated circuit 8 channels per chip

12b ADC 7 Analog Electronics Upgrade Motivation PMT current has to be reduced to increase lifetime ⇒ FE electronics gain has to be increased correspondingly –BUT FE noise should not be increased in the operation! Noise < 1 ADC Count –For 12 bit DR, input referred noise <1nV/sqrt(Hz) ⇒ Termination resistor at input generates too much noise 24 th April 2013CHEF 2013 Detector cells clip 12m cable -+-+ PMT 5ns 50Ω 50Ω 25ns 100Ω 100Ω BUFFER R f = 12MΩ C f = 4pF 100nF 22nF INTEGRATOR Analog Chip Solutions: –New ASIC Increased gain Active cooled termination –Discrete solution: Components Out-of-The-Shelf (COTS) 2/3 of the signal are lost by clipping Remove clipping at the PM base (detector) Perform clipping after amplification in FE using delay lines Discrete solution (COTS) Front End Board

8 ASIC Channel Architecture Very difficult to integrate in ASIC HQ analog delay lines 2 switched alternated paths* Switching noise! Fully diferential ASAP 24 th April 2013CHEF 2013 * Used successfully in LHCb PS/SPD Calo Current Amplifier → Active cooled termination Switched Integrator → Fully differential OpAmp Track-and-Hold → Flip-around architecture ADC driver → to match ADC impedance Analog Multiplexer Two prototypes already designed and tested: –Preamp + integrator –Preamp + integrator + TH Technology: –SiGe BiCMOS 0.35um AMS

9 COTS Channel Architecture 24 th April 2013CHEF 2013 PMT signal Clipped signal Integral AMP Clipping Line Clipped signal Delayed and inverted clipped signal

10 Front End Board Prototype Tests 24 th April 2013CHEF 2013 Delay Chips Analog Mezzanine (ASIC/COTS) FPGA Actel A3PE1500 Verilog blocks: USB and control board General functionality DAQ USB PC with CAT sw Control and data acquisition WAVEFORM GENERATOR Test signal Tests: –Linearity –Noise –Integral plateau –Spill over NIM I/O Regulators

11 Test Beam Measurements (Nov. 2012) Used e- of 50 to 125GeV Measurements: –Noise after pedestal subtraction: ~1.6 ADC (ASIC) and ~2.6 ADC (COTS) 24 th April 2013CHEF 2013 ECAL channel+PMT+same 12m cable Noise (ASIC)

12 Test Beam Measurements (Nov. 2012) Measurements (cont’d): –Linearity better than 1% –Integral plateau ~1.6% at ±2ns (ASIC) and <1% (COTS) –Spill over of ~8% in following sample (ASIC) Cable effect on signal was underestimated: –Affects plateau and spill over ⇒ Pole-zero filter proposed for next version of ASIC/COTS 24 th April 2013CHEF 2013 ADC FE ADC Lecroy Plateau (COTS) Linearity (ASIC) Measured clipped signal Clipped signal after PZ filter

13 Summary Upgrade architecture with new Front-End electronics board –40MHz readout –Re-use FE crate –Actel FPGA reprogrammable A3PE family Analog shaping electronics: two solutions –ASIC: cooled input termination for reduced noise 2 interleaved channels and switched integrators: no deadtime Full 4 channel ASIC to be sent in June 2013 –Discrete elements (COTS): Clipping removed from PMT base and installed in the FEB: increase in signal Definitive version scheduled by end of May 2013 –Final decision before September 2013 Prototypes positively tested both at lab and at a test beam Technical Design Report (TDR): September th April 2013CHEF 2013

14 Back up 24 th April 2013CHEF 2013

15 Current Trigger and Readout Architecture 24 th April 2013CHEF 2013 WALLWALL L1, HLT, DAQ TTC, ECS

16 Upgrade Architecture 24 th April 2013CHEF 2013