® Virtex-E Extended Memory Technical Overview and Applications

® BRAM CLBs BRAM XCV812E 0 Virtex-E Extended Memory  CLB Array is 56 height and 84 wide  Same architecture as Virtex-E —BRAM starts at both sides —Each block is 4 CLBs high  Except —BRAM is inserted every 4th CLB column —Except for the middle 12 columns of CLBs

® Virtex-E Extended Memory  14 blocks per column and 20 columns total (starting with 0) = 280 blocks  280 blocks x 4096 bits = (1120K) bits of total BRAM  XCV600E has 72 blocks and XCV1000E has 96 blocks

® BRAM CLBs CLBs BRAM XCV405E 0 Virtex-E Extended Memory  CLB Array is 40 height and 60 wide  Same architecture as Virtex E —BRAM starts at both sides —Each block is 4 CLBs high  Except —BRAM is inserted every 4th CLB column —Except for the middle 12 columns of CLBs

® Virtex-E Extended Memory  10 blocks per column and 14 columns total (starting with 0) = 140 blocks  140 blocks x 4096 bits = (560K) bits of total BRAM  XCV400E has 40 blocks

® Virtex-EM Applications  Video and image enhancement  Larger memory-to-logic ratio required by some DSP functions  Improved memory bandwidth for high performance video applications  2D FIR Filter with on-board line buffers used in image processing

® PCI VRAM JPEG 2D FIR Miixer Field Buffer Resize VIDEO VRAM Potential Applications Image Enhancement

® Line of N pixels M bits wide N lines per image Basic Operation  Square kernel mask is moved across an image pixel-by- pixel and line-by-line  New center pixel is created based on neighborhood  Kernel masks of various sizes Image

® C3 C2 C1 Line Buffers From Frame Buffer Basic Operation  Line buffers store one line of pixels  Line buffers dramatically reduce pin count  Coefficients are symmetric for most video filters  Each pixel is multiplied by a coefficient  Pixels are summed and create a new center pixel value

®  Vertical and horizontal FIR filters are shared through muxing  Typical image is 1024x1024x12 (8) (e.g. Medical Graphics)  Typical kernel is up to 15x15 ( 196,608 Bits=Virtex E)  In high end applications 31x31 (393,216 Bits=Virtex EM 405)  Or even 63x63 are desirable (786,432 Bits=Virtex EM 812) 2D FIR Filter with build-in Buffers

® Implementation Block Diagram

® RAM Requirements Pixels per Line Bits per Pixel XCV405EXCV812E Number of lines 12 bits/pixel

® Conclusion  High performance arithmetic functions allow logic to be shared  On-chip line buffers improve performance and reduce the number of IO required  More functions can be integrated on the same chip  Large memory to logic ratio enables high end graphic systems  High memory bandwidth

® 16 x16 OC-192 Buffered Crossbar Switch Virtex-EM Applications

® N x N Buffered Crossbar Switch  N input ports and N output ports are connected through an N x N matrix of switching elements  Buffers, typically FIFOs are at the core of the switching element  Output port contention addressed by storing packets in FIFOs at each crosspoint  Reduced Head-of-Line (HOL) blocking  Increased thoughput

® 16x16 OC-192 Buffered Crossbar Switch using XCV812E devices

® Switch Performance  Speed requirements —For each port, 128-bit data is sliced into 16 8-bit slices. Each data slice is processed by a XCV812E device —OC-192 line rate = 10Gbit/sec —Byte-wide FIFOs must run at 10/128 = 78 MHz minimum —With internal speedup factor, required FIFO speed > 78 MHz  XCV812E supports > 150 MHz FIFOs  Switch speed = 16 ports x 10 Gbit/sec/port = 160 Gbit/sec is easily achieved

® Switch Performance (contd.)  Memory requirements —Min. buffer size = 2 * port-speed/per-slice * round-trip delay in the control feedback signal —For OC Gbit/sec, 16 data slices, 800ns (approx.) round trip delay: –Min. buffer size = 2 x10 Gb/s x 800ns / 16 = 1000 bits —Total buffer memory needed = 16 x 16 x 1 Kb —Total number of buffers = 256 x 1Kb buffers  XCV812E has 280 blocks of 4Kb Block RAM

® Floorplan Layout of the Design

® Conclusion  Virtex-EM architecture and features are highly suited to the buffered crossbar switch application  High ratio of Block SelectRAM to logic  Select I/O+; up to 20 I/O standards including differential signaling standards supported  High speed synchronous (>150 MHz) FIFOs