Algorithmic State Machines Sorting Signed & Unsigned Data Types ECE 545 Lecture 10 Algorithmic State Machines Sorting Signed & Unsigned Data Types ECE 545 – Introduction to VHDL

Sources & Required Reading Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 8.10 Algorithmic State Machine (ASM) Charts Chapter 10.2.6 Sort Operation Sundar Rajan, Essential VHDL, Chapter 5 Counters and Simple Arithmetic Functions ECE 545 – Introduction to VHDL

Algorithmic State Machine (ASM) Charts ECE 545 – Introduction to VHDL

Algorithmic State Machine representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables. ECE 545 – Introduction to VHDL

Elements used in ASM charts (1) State name Output signals 0 (False) 1 (True) Condition or actions expression (Moore type) (a) State box (b) Decision box Conditional outputs or actions (Mealy type) (c) Conditional output box ECE 545 – Introduction to VHDL

Elements used in ASM charts (2) State box – represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place. ECE 545 – Introduction to VHDL

Elements used in ASM charts (3) Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordingly The condition expression consists of one or more inputs to the FSM. Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box. ECE 545 – Introduction to VHDL

Moore FSM – Example 1: State diagram C z 1 = ¤ Reset B A w ECE 545 – Introduction to VHDL

ASM Chart for Moore FSM – Example 1 ECE 545 – Introduction to VHDL

Mealy FSM – Example 2: State diagram w = z ¤ 1 B Reset ECE 545 – Introduction to VHDL

ASM Chart for Mealy FSM – Example 2 ECE 545 – Introduction to VHDL

Control Unit - Example 3 ECE 545 – Introduction to VHDL

ASM Chart for Control Unit - Example 3 ECE 545 – Introduction to VHDL

Sorting ECE 545 – Introduction to VHDL

Pseudocode for the sort operation = to k 2 do A R ; j + 1 B if < then end if end for; – ECE 545 – Introduction to VHDL

ASM chart for the sort operation ECE 545 – Introduction to VHDL

Datapath Circuit for the sort operation ECE 545 – Introduction to VHDL

Control Circuit – Part 1 ECE 545 – Introduction to VHDL

ASM chart for the Control Circuit – Part 2 ECE 545 – Introduction to VHDL

VHDL code (1) – Entity declaration LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.components.all ; ENTITY sort IS GENERIC ( N : INTEGER := 4 ) ; PORT (Clock, Resetn : IN STD_LOGIC ; s, WrInit, Rd : IN STD_LOGIC ; DataIn : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; RAdd : IN INTEGER RANGE 0 TO 3 ; DataOut : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Done : BUFFER STD_LOGIC ) ; END sort ; ECE 545 – Introduction to VHDL

Package components (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE components IS -- n-bit register with enable COMPONENT regne GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn : IN STD_LOGIC ; E : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; ECE 545 – Introduction to VHDL

Package components (2) -- up-counter that counts from 0 to modulus-1 COMPONENT upcount GENERIC ( modulus : INTEGER := 8 ) ; PORT ( Resetn : IN STD_LOGIC ; Clock : IN STD_LOGIC ; E : IN STD_LOGIC ; L : IN STD_LOGIC ; R : IN INTEGER RANGE 0 TO modulus-1 ; Q : BUFFER INTEGER RANGE 0 TO modulus-1 ) ; END COMPONENT ; END components ; ECE 545 – Introduction to VHDL

Datapath Circuit for the sort operation ECE 545 – Introduction to VHDL

VHDL code (2) – Datapath signal declarations ARCHITECTURE Dataflow OF sort IS -- datapath data buses TYPE RegArray IS ARRAY(3 DOWNTO 0) OF STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; SIGNAL R : RegArray; SIGNAL RData : STD_LOGIC_VECTOR(N-1 DOWNTO 0); SIGNAL ABData : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; SIGNAL A, B : STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; SIGNAL ABMux : STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- datapath control signals SIGNAL Rin : STD_LOGIC_VECTOR(3 DOWNTO 0) ; SIGNAL IMux : INTEGER RANGE 0 TO 3 ; SIGNAL Ain, Bin : STD_LOGIC ; SIGNAL Aout, Bout : STD_LOGIC ; SIGNAL BltA : STD_LOGIC ; ECE 545 – Introduction to VHDL

Control Circuit – Part 1 ECE 545 – Introduction to VHDL

VHDL code (3) – Control unit signal declarations -- control unit Part 1 SIGNAL Zero : INTEGER RANGE 3 DOWNTO 0 ; SIGNAL Ci, Cj : INTEGER RANGE 0 TO 3 ; SIGNAL CMux : INTEGER RANGE 0 TO 3 ; SIGNAL LI, LJ : STD_LOGIC ; SIGNAL EI, EJ : STD_LOGIC ; SIGNAL zi, zj : STD_LOGIC ; SIGNAL Csel : STD_LOGIC ; SIGNAL Int : STD_LOGIC ; SIGNAL Wr : STD_LOGIC ; -- control unit Part 2 TYPE State_type IS ( S1, S2, S3, S4, S5, S6, S7, S8, S9 ); SIGNAL y : State_type; ECE 545 – Introduction to VHDL

Datapath Circuit for the sort operation ECE 545 – Introduction to VHDL

VHDL code (4) - Datapath BEGIN RData <= ABMux WHEN WrInit = '0' ELSE DataIn ; GenReg: FOR i IN 0 TO 3 GENERATE Reg: regne GENERIC MAP ( N => N ) PORT MAP ( R => RData, Resetn => Resetn, E => Rin(i), Clock => Clock, Q => R(i) ) ; END GENERATE ; WITH IMux Select ABData <= R(0) WHEN 0, R(1) WHEN 1, R(2) WHEN 2, R(3) WHEN OTHERS ; ECE 545 – Introduction to VHDL

VHDL code (5) - Datapath RegA: regne GENERIC MAP ( N => N ) PORT MAP ( R => ABData, Resetn => Resetn, E => Ain, Clock => Clock, Q => A ) ; RegB: regne GENERIC MAP ( N => N ) E => Bin, Q => B ) ; BltA <= '1' WHEN B < A ELSE '0' ; ABMux <= A WHEN Bout = '0' ELSE B ; DataOut <= (OTHERS => 'Z') WHEN Rd = '0' ELSE ABData ; ECE 545 – Introduction to VHDL

Control Circuit – Part 1 ECE 545 – Introduction to VHDL

VHDL code (6) – Control Unit Part 1 Zero <= 0 ; OuterLoop: upcount GENERIC MAP ( modulus => 4 ) PORT MAP ( Resetn => Resetn, Clock => Clock, E => EI, L => LI, R => Zero, Q => Ci ) ; InnerLoop: upcount GENERIC MAP ( modulus => 4 ) E => EJ, L => LJ, R => Ci, Q => Cj ) ; ECE 545 – Introduction to VHDL

VHDL code (7) – Control Unit Part 1 CMux <= Ci WHEN Csel = '0' ELSE Cj ; IMux <= Cmux WHEN Int = '1' ELSE Radd ; RinDec: PROCESS ( WrInit, Wr, IMux ) BEGIN IF (WrInit OR Wr) = '1' THEN CASE IMux IS WHEN 0 => Rin <= "0001" ; WHEN 1 => Rin <= "0010" ; WHEN 2 => Rin <= "0100" ; WHEN OTHERS => Rin <= "1000" ; END CASE ; ELSE Rin <= "0000" ; END IF ; END PROCESS ; Zi <= '1' WHEN Ci = 2 ELSE '0' ; Zj <= '1' WHEN Cj = 3 ELSE '0' ; ECE 545 – Introduction to VHDL

ASM chart for the Control Circuit – Part 2 ECE 545 – Introduction to VHDL

VHDL code (8) – Control Unit Part 2 FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= S1 ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN S1 => IF S = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ; WHEN S2 => y <= S3 ; WHEN S3 => y <= S4 ; WHEN S4 => y <= S5 ; WHEN S5 => IF BltA = '1' THEN y <= S6 ; ELSE y <= S8 ; END IF ; WHEN S6 => y <= S7 ; WHEN S7 => y <= S8 ; WHEN S8 => IF zj = '0' THEN y <= S4 ; ELSIF zi = '0' THEN y <= S2 ; ELSE y <= S9 ; END IF ; WHEN S9 => IF s = '1' THEN y <= S9 ; ELSE y <= S1 ; END IF ; END CASE ; END PROCESS ; ECE 545 – Introduction to VHDL

VHDL code (9) – Control Unit Part 2 -- define the outputs generated by the FSM Int <= '0' WHEN y = S1 ELSE '1' ; Done <= '1' WHEN y = S9 ELSE '0' ; FSM_outputs: PROCESS ( y, zi, zj ) BEGIN LI <= '0' ; LJ <= '0' ; EI <= '0' ; EJ <= '0' ; Csel <= '0' ; Wr <= '0'; Ain <= '0' ; Bin <= '0' ; Aout <= '0' ; Bout <= '0' ; CASE y IS WHEN S1 => LI <= '1' ; EI <= '1' ; WHEN S2 => Ain <= '1' ; LJ <= '1' ; EJ <= '1' ; WHEN S3 => EJ <= '1' ; WHEN S4 => Bin <= '1' ; Csel <= '1' ; WHEN S5 => -- no outputs asserted in this state WHEN S6 => Csel <= '1' ; Wr <= '1' ; Aout <= '1' ; WHEN S7 => Wr <= '1' ; Bout <= '1' ; ECE 545 – Introduction to VHDL

VHDL code (10) – Control Unit Part 2 WHEN S8 => Ain <= '1' ; IF zj = '0' THEN EJ <= '1' ; ELSE EJ <= '0' ; IF zi = '0' THEN EI <= '1' ; EI <= '0' ; END IF; END IF ; WHEN S9 => -- Done is assigned 1 by conditional signal assignment END CASE ; END PROCESS ; END Dataflow ; ECE 545 – Introduction to VHDL

Simulation results for the sort operation (1) Loading the registers and starting sorting ECE 545 – Introduction to VHDL

Simulation results for the sort operation (2) Completing sorting and reading out registers ECE 545 – Introduction to VHDL

Alternative datapath based on tri-state buffers ECE 545 – Introduction to VHDL

Arithmetic mean ECE 545 – Introduction to VHDL

Pseudocode for the mean of k numbers Sum = 0 for i = k - 1 downto 0 do Sum = Sum + Ri end for M = Sum / k ECE 545 – Introduction to VHDL

ASM chart for the mean of k numbers ECE 545 – Introduction to VHDL

Datapath & Control Circuit ECE 545 – Introduction to VHDL

ASM chart for the control circuit ECE 545 – Introduction to VHDL

Schematic with an SRAM block ECE 545 – Introduction to VHDL

Simulation results for the mean circuit ECE 545 – Introduction to VHDL

Clock skew and metastability ECE 545 – Introduction to VHDL

Flip-flop enable – incorrect approach D Q Data Clock E ECE 545 – Introduction to VHDL

Flip-flop enable – correct approach D Q R Clock E 1 ECE 545 – Introduction to VHDL

An H tree clock distribution network ff ECE 545 – Introduction to VHDL

Arithmetic and Relational in Predefined Packages Operators in Predefined Packages ECE 545 – Introduction to VHDL

std_logic_unsigned / std_logic_signed Operand 1 Operand Operand 2 Result +  * std_logic_vector std_logic integer std_logic_vector std_logic integer std_logic_vector ECE 545 – Introduction to VHDL

Different declarations for the same operator - Example Declarations in the package ieee.std_logic.unsigned: function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector; ECE 545 – Introduction to VHDL

Different declarations for the same operator - Example signal count: std_logic_vector(7 downto 0); You can use: count <= count + “0000_0001”; or count <= count + 1; count <= count + ‘1’; ECE 545 – Introduction to VHDL

Signed and unsigned data types signed, unsigned - represent an array of std_logic values (the same as std_logic_vector) - allow a user to indicate which representation unsigned or signed 2’s complement is being used ECE 545 – Introduction to VHDL

std_logic_arith Operand 1 Operand Operand 2 Result +  * signed unsigned integer std_logic +  * signed unsigned integer std_logic signed unsigned std_logic_vector ECE 545 – Introduction to VHDL

std_logic_arith Operand 1 Operand Operand 2 Result > < = >= <= /= signed unsigned integer signed unsigned integer boolean ECE 545 – Introduction to VHDL

numeric_std Operand 1 Operand Operand 2 Result +  * ** / mod signed unsigned integer natural signed unsigned integer natural signed unsigned Not synthesizable unless constant operands or division by a power of 2 ECE 545 – Introduction to VHDL

numeric_std Operand 1 Operand Operand 2 Result > < = >= <= /= signed unsigned integer natural signed unsigned integer natural boolean ECE 545 – Introduction to VHDL

Modulo-11 down-counter (1) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity downCounter is port ( clk: in std_logic; reset: in std_logic; count: out std_logic_vector(3 downto 0) ); end downCounter; ECE 545 – Introduction to VHDL

Modulo-11 down-counter (2) architecture simple of downCounter is signal countL: unsigned(3 downto 0); signal termCnt: std_logic; begin decrement: process (clk, reset) begin if (reset = '1') then countL <= "1011"; -- Reset to 11 termCnt <= '1'; elsif(clk'event and clk = '1') then if (termCnt = '1') then countL <= "1011"; -- Count rolls over to 11 else countL <= countL - 1; end if; ECE 545 – Introduction to VHDL

Modulo-11 down-counter (3) if (countL = "0001") then -- Terminal count decoded 1 cycle earlier termCnt <= '1'; else termCnt <= '0'; end if; end process; count <= std_logic_vector(countL); end simple; ECE 545 – Introduction to VHDL

Modulo-11 down-counter with to_unsigned architecture simple of downCounter is signal countL: unsigned(3 downto 0); signal termCnt: std_logic; begin decrement: process (clk, reset) begin if (reset = '1') then countL <= to_unsigned(11, 4); -- Reset to 11 termCnt <= '1'; elsif(clk'event and clk = '1') then if (termCnt = '1') then countL <= "1011"; -- Count rolls over to 11 else countL <= countL - 1; end if; ECE 545 – Introduction to VHDL