2009/2/10NTUEE Research Projects1 Applied Logic & Computation in System Design - A Research Invitation Jie-Hong R. Jiang 江介宏 NTUEE/GIEE National Taiwan.

Slides:

Advertisements

Similar presentations

The Synthesis of Cyclic Circuits with SAT and Interpolation By John Backes and Marc Riedel ECE University of Minnesota.

Advertisements

Local Computation Algorithms

The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota.

Reduction of Interpolants for Logic Synthesis John Backes Marc Riedel University of Minnesota Dept.

Challenges to the Modern Synthesis Stephen Jay Gould, Nils Eldredge,

1 Boolean Satisfiability in Electronic Design Automation (EDA ) By Kunal P. Ganeshpure.

Ren-Song Tsay NTUEE NTUEE UC Berkeley, Ph.D. UC Berkeley, Ph.D. IBM T.J. Watson Research Center IBM T.J. Watson Research Center ArcSys – world first successful.

Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical.

Bounded Model Checking EECS 290A Sequential Logic Synthesis and Verification.

Gene Regulatory Networks - the Boolean Approach Andrey Zhdanov Based on the papers by Tatsuya Akutsu et al and others.

 Y. Hu, V. Shih, R. Majumdar and L. He, “Exploiting Symmetries to Speedup SAT-based Boolean Matching for Logic Synthesis of FPGAs”, TCAD  Y. Hu,

03/08/2005 © J.-H. Jiang1 Retiming and Resynthesis EECS 290A – Spring 2005 UC Berkeley.

USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,

Using Mathematica for modeling, simulation and property checking of hardware systems Ghiath AL SAMMANE VDS group : Verification & Modeling of Digital systems.

Faster Logic Manipulation for Large Designs Alan Mishchenko Robert Brayton University of California, Berkeley.

Electrical and Computer Engineering Archana Rengaraj ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011.

Combinational Problems: Unate Covering, Binate Covering, Graph Coloring and Maximum Cliques Example of application: Decomposition.

Combinational and Sequential Mapping with Priority Cuts Alan Mishchenko Sungmin Cho Satrajit Chatterjee Robert Brayton UC Berkeley.

ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center Robert Brayton, Niklas Een, Alan Mishchenko,

Section 2 CHAPTER 10. PROTEIN SYNTHESIS IN PROKARYOTES Both prokaryotic and eukaryotic cells are able to regulate which genes are expressed and which.

PhD Projects Rahul Santhanam University of Edinburgh.

A Genetic Differential Amplifier: Design, Simulation, Construction and Testing Seema Nagaraj and Stephen Davies University of Toronto Edward S. Rogers.

Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.

1 Stephen Jang Kevin Chung Xilinx Inc. Alan Mishchenko Robert Brayton UC Berkeley Power Optimization Toolbox for Logic Synthesis and Mapping.

1 Alan Mishchenko Research Update June-September 2008.

2009/6/30 CAV Quantifier Elimination via Functional Composition Jie-Hong Roland Jiang Dept. of Electrical Eng. / Grad. Inst. of Electronics Eng.

A Semi-Canonical Form for Sequential Circuits Alan Mishchenko Niklas Een Robert Brayton UC Berkeley Michael Case Pankaj Chauhan Nikhil Sharma Calypto Design.

Towards Completely Automatic Decoder Synthesis Hsiou-Yuan Liu, Yen-Cheng Chou, Chen- Hsuan Lin, and Jie-Hong Roland Jiang ALCom Lab EE Dept/ Grad. Inst.

Speaker: Nansen Huang VLSI Design and Test Seminar (ELEC ) March 9, 2016 Simulation-Based Equivalence Checking.

Resolution Proofs as a Data Structure for Logic Synthesis John Backes Marc Riedel Electrical.

4/11/2005 Applied Logic & Computation for System Design - An introductory invitation Jie-Hong R. Jiang 江介宏 National Taiwan University.

Reducing Structural Bias in Technology Mapping

Hardware Acceleration of A Boolean Satisfiability Solver

Synthesis for Verification

Technology Mapping into General Programmable Cells

Power Optimization Toolbox for Logic Synthesis and Mapping

Delay Optimization using SOP Balancing

James D. Z. Ma Department of Electrical and Computer Engineering

Enhancing PDR/IC3 with Localization Abstraction

SAT-Based Logic Optimization and Resynthesis

Robert Brayton Alan Mishchenko Niklas Een

New Directions in the Development of ABC

Alan Mishchenko Robert Brayton UC Berkeley

Magic An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko UC Berkeley.

Robert Brayton Alan Mishchenko Department of EECS UC Berkeley

Versatile SAT-based Remapping for Standard Cells

Example of application: Decomposition

A Boolean Paradigm in Multi-Valued Logic Synthesis

Synthesis for Verification

SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere

The Synergy between Logic Synthesis and Equivalence Checking

Fast Computation of Symmetries in Boolean Functions Alan Mishchenko

Canonical Computation without Canonical Data Structure

Canonical Computation Without Canonical Data Structure

Scalable and Scalably-Verifiable Sequential Synthesis

Mapping into LUT Structures

SAT-based Methods for Scalable Synthesis and Verification

Resolution Proofs for Combinational Equivalence

SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere!)

Canonical Computation without Canonical Data Structure

SAT-Based Logic Synthesis

Delay Optimization using SOP Balancing

Robert Brayton Alan Mishchenko Department of EECS UC Berkeley

Canonical Computation without Canonical Data Structure

Magic An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko UC Berkeley.

Innovative Sequential Synthesis and Verification

Robert Brayton Alan Mishchenko Niklas Een

Jie-Hong R. Jiang 江介宏 DEE/GIEE National Taiwan University

Robert Brayton Alan Mishchenko Niklas Een

SAT-Based Logic Synthesis

Presentation transcript:

2009/2/10NTUEE Research Projects1 Applied Logic & Computation in System Design - A Research Invitation Jie-Hong R. Jiang 江介宏 NTUEE/GIEE National Taiwan University TexPoint fonts used in EMF. Read the TexPoint manual before you delete this box.: A A

2009/2/10NTUEE Research Projects2 ALCom Lab Founded in Aug Rm. 526, Ming-Dar Hall Lab of cool ideas  A creative research environment Crazy ideas encouraged!

2009/2/10NTUEE Research Projects3 Research focuses Logic  Formal verification and logic synthesis Scalable techniques Synergy between the two Optimization  Statistical methods for nanometer IC design  Optimization methods and their applications Foundations  New computation models

2009/2/10NTUEE Research Projects4 Recent publications [1] To SAT or Not to SAT: Ashenhurst Decomposition in a Large Scale. ICCAD'08 Joint work with Hsuan-Po Lin, Ruei-Rung Lee [2] Bi-Decomposing Large Boolean Functions via Interpolation and Satisfiability Solving. DAC’08 Joint work with Ruei-Rung Lee, Wei-Lun Hung [3] Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving. ICCAD'07 best paper nominee Joint work with Chih-Chun Lee, Chung-Yang (Ric) Huang, Alan Mishchenko [4] Inductive Equivalence Checking under Retiming and Resynthesis. ICCAD'07 Joint work with Wei-Lun Hung [5] SAT-based Logic Optimization and Resynthesis. IWLS'07 Joint work with Alan Mishchenko, Robert Brayton, Stephen Jang [6] A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS'07 Joint work with Chin-Hsiung Hsu, Szu-Jui Chou, Yao-Wen Chang [7] Quantum Mechanical Search and Harmonic Perturbation. Quantum Information Processing, 2007 Joint work with Dah-Wei Chiou, Cheng-En Wu

2009/2/10NTUEE Research Projects5 Who are qualified? Whoever interested in  switching circuits / logic design,  computer programming,  discrete math,  algorithms, OR  electronic design automation (EDA)

2009/2/10NTUEE Research Projects6 Uniqueness Take on important problems which may yield substantial impacts on industry and academia Work closely with the coach  Gain great research advice and learn a lot Learn what PhD students are doing!  Not just waste your labor

2009/2/10NTUEE Research Projects7 Project 1: Biological Circuit Analysis metabolic networks signal transduction networks gene regulatory networks

2009/2/10NTUEE Research Projects8 Project 1: Biological Circuit Analysis DNA gene y mRNA promoter transcription translation protein Y protein X X* X can be an activator or a repressor of Y: X Y

2009/2/10NTUEE Research Projects9 Project 1: Biological Circuit Analysis Gene regulatory networks are similar to logic circuits! Source: An Intro. to Systems Biology by U. Alon

2009/2/10NTUEE Research Projects10 Project 1: Biological Circuit Analysis We’ll apply logic circuit analysis and optimization techniques to biological circuit analysis and design.

2009/2/10NTUEE Research Projects11 Project 2: Symmetry Detection Using SAT Solving If f(x,y) = f(y,x), then function f is symmetric on variables x and y We’ll design algorithms to solve this problem for functions with up to hundreds or even thousands of variables

2009/2/10NTUEE Research Projects12 Project 3: Circuit Optimization via Functional Dependency and Decomposition Recent work showed an effective way of computing functional dependency and decomposition We’ll use them in the application of circuit optimization

2009/2/10NTUEE Research Projects13 Contact info ALCom Lab Rm. 526, MD Hall (02) Jie-Hong R. Jiang Rm. 242, EEII Building (02)

2009/2/10NTUEE Research Projects14 Thank you!