The Past... DDL in ALICE DAQ The DDL project ( )  Collaboration of CERN, Wigner RCP, and Cerntech Ltd.  The major Hungarian engineering contribution to the LHC experiments HLT Farm H-RORC FEP D-RORC LDC D-RORC LDC DIU SIU Event Building Network Readout Electronics TPC Sub-Detector D-RORC LDC DIU SIU Readout Electronics Sub-Detectors DIU SIU DIU SIU Source Interface Units (SIU cards) Duplex, multimode optical fibers max. 200m Destination Interface Units (integrated on D-RORCs) DAQ- Readout Receiver Card Local Data Concentrators (server computers) GDC Global Data Collectors (server computers) 144 DDL 216 DDL 10 DDLs (Gigabit Ethernet and FibreChannel switches) 487 DDL optical links High- Level Trigger Storage Network (disk farms, tapes) ALICE sub-detectors 25 GB/s total 127 DDL

DDL Hardware 32-bit parallel interface Duplex LC optical connector Radiation tolerant FPGA design DDR3 Memory x8, Gen2 PCI Express interface 12 DDL links up to 6 Gb/s

The Future... The ALICE Online & Offline Upgrade (O2) Project FTP LTU DCS Server DAQ/HLT EPN DAQ/HLT Network DAQ/HLT Network DCS Network DCS Network DCS Server Data + Control Data traffic Embedded or separated Data + Trig.+ Ctrl. Control PON Trigger & Busy Rad Hard FE Links (copper or fibre) FLP w/ or w/o DPRM (DAQ or HLT) DAQ/HLT Network DAQ/HLT Network High-performance DDL3 (fibre) On-line Computing Node w/ DPR (DAQ + HLT) On-line Computing Node w/ DPR (DAQ + HLT) Front-End Common Read-out Unit (CRU) (some DPR is possible!) Common Read-out Unit (CRU) (some DPR is possible!) custom hw + fw if needed, incl. I/O and/or DPR card (or may be all commercial) custom hw + fw (industrial standard) Budapest role (main points): Taking part in R&D of architecture and topology R&D of dataflow and MM algorithms (sw) Design of the necessary custom hw + fw components of the common part of the system (dataflow part, green in the diagram) custom hw + fw if needed, incl. I/O and/or DPR card (or may be all commercial) custom hw + fw (industrial standard) detectors

Our Contribution to ALICE Online and Offline Upgrade (O2) Project Fields:  SW development  Read-out Perfomance tests: I/O and memory bandwidth tests  Custom HW development (links, I/O interfaces, DPRM cards)  Custom HW development (front-end electronics) SW (+FW) development, support:  Continuous in short, mid, and long-term  Experts, contact persons: Ervin Dénes, Gábor Kiss Read-out Performance tests:  Together w/ ALICE DAQ group (c.p.: Filippo Costa)  Experts, contact person: Ervin Dénes HW and FW development  Rich experience from the past (HW: Budapest, FW: Budapest + CERN)  Experts, contact person: Tivadar Kiss, Tamás Tölyhi, Ernő Dávid (Cerntech)

Possible Contributions / II. HW (+FW) development: front-end electronics upgrades  We offer our services in designing electronics with ADCs, 10Gb/s PHY, and FPGAs for sub-detectors lacking of manpower (or competence)  Limitation: no experience in ASIC (IC) design  Ongoing project: The new Read-out Concentrator Unit (RCU2) board design for the TPC detector consolidation project during LS1 (for Run2) o PCB design to be finished this year, Prototyping, testing, modifications, production: HW (+ FW) development: links, I/Os, DPRM („DDL3”, RORC3”)  Rich experience from the past with custom FPGA cards, but... is there a need for custom hardware in the future?  Hardware and Firmware development largely depends on the technology choosen finally by ALICE  Ongoing project: Leading the project of the development of the Common Read-out Unit (CRU) for ALICE O2 Upgrade (for Run3) o VECC (Kolkata) has just joined the project with FW developers (Tapan Nayak, Shuaib A. Khan, et co.)