Characterization of irradiated MOS-C with X-rays using CV-measurements and gated diode techniques Q. Wei, L. Andricek, H-G. Moser, R. H. Richter, Max-Planck-Institute for Physics Semiconductor Laboratory

Motivation Experimental conditions Study of the radiation damage by CV- measurements and gated diode technique, annealing behavior at RT, comparison of extracted N ox, N it values Discussion of the results Outline

Radiation damage of semiconductor devices (e.g. DEPFET) Study on the radiation damage with MOS-C using CaliFa teststand at MPI HLL Munich Comparison of results from two different measurement methods (MOS-C and gated diode) Motivation

Comparison between different semiconductor devices MOS-CGated diodeDEPFET N ox (method) ΔV FB (CV- Measurement) ∆V FB & ∆V g (CV-Measurement & gated diode technique) Δ V t (IV-Measurement) N it (method) Stretchout (High-low frequency based on the CV) Full width at 2/3 maximal of current (gated diode technique) Subthreshold slope (Subthreshold technique) Other parameters S 0, σ n/p & (gated diode technique) g m (IV-Measurement) (Only for the 1-D defects) 0 

Irradiation: X-Ray tube with Mo target at 30kV and 30mA (17,44keV & Bremsstrahlung ) dose: 1 week of irradiation up to 1M rad, dose rate: 2.5rad/s (1rad=0.01J/kg) Samples: –Based on n-type high resistance silicon(450  m) wafer: doping concentraion ~ cm -3 Bias conditions: +5V,0V,-5V for MOS-C; 0V for gated diode Measurements: –CV: HF (10kHz); LF (20Hz) all values in series mode (C s, R s ) –Gated diode: V Al : 10V, V edge : 0.25V, V Al/Poly : from positive to negative values –Annealing: at RT for about 5 days on MOS-C and 10 days on Gated Diode Experimental Conditions

Substrate Substrate Poly1/Poly2 Aluminium LTO Oxide Ni Cross section and layout of MOS-C Poly1/2 Al –MOS-C: –the upper left – Al1 –the upper right – Al2 –the lower left –Poly1 –the lower right –Poly2 –each contact area is about 10 mm 2 Al2

For MOS-C extracted results for MOS-C & Gated Diode CV-Measurement Gate Bias conditions: 0V

For MOS-C Flat band voltage Shift  N ox high-low frequency CV  N it CV-Measurement Gate Bias conditions: 0V

Annealing for MOS-C Gate bias conditions: 0V During annealing N ox decreases linearly with ln(t) Weak annealing (~25%) (~6,5%)

For MOS-C Due to too large leakage current at dose 200krad CV-Measurement does not work Gate bias conditions: +5V literatur: Interface trap will not saturate at dose of 1Mrad!

Gate bias conditions: -5V For MOS-C

Much more defects (N ox,N it ) for positive gate than for 0V bias both poly-gate and Al- gate structure More defects for Al-gate than poly-gate Almost the same amount of defects (N ox,N it ) for negative gate bias as for 0V both poly- gate and Al-gate structure V G at +5V Vs. V G at 0V V G at -5V Vs. V G at 0V For any given V G

Cross section structure and layout for gated diode P+ Al/Poly Gate A AlAl Substrate V Edg e N V Erd e 5µm5µm 95µm Poly-gate Al-gate Al P+ grounding Edge Al P+ gated diode wafer the left one – Al the right one –poly each area is 9 mm 2

For gated Diode peak shift  N ox Full width at 2/3 I max  N it By using gated diode technique Gate bias conditions: 0V ?

Using CV-method (HF) For gated Diode Gate bias conditions: 0V A good agreement for determination of N ox by ΔV FB (CV) and ΔV G (gated diode technique)

Annealing for Gated Diode During annealing N ox decreases linearly with ln(t) Weak annealing Using gate controlled diode technique Small fraction of positive oxide charges (~11%) are recoverd! Gate bias conditions: 0V

for Gated Diode Gate bias conditions: 0V (due to another traps)

GSF – National Research Center for Environment and Health, Munich 60 Co (1.17 MeV and 1.33 MeV) "OFF" "ON" Bias during irradiaton: 1: empty int. gate, in „off“ state, V GS = 5V, V Drain =-5V  E ox ≈ 0 2:empty int. gate, in „on“ state, V GS =-5V, V Drain =-5V  E ox ≈ -250kV/cm 3: all terminals at 0V Results for DEPFET 1.postive oxide charge: negative shift of the theshold voltage (~t ox 2 ) 2.interface traps: higher 1/f noise and reduced mobility (g m ) No annealing during irradiation  ~ 3 days irradiation Radiation Effects (ionizing radiation)

Transconductance and subtreshold slope s=85mV/dec s=155mV/dec V th =-0.2V V th =-4.5V Literature: After 1Mrad 200 nm (SiO 2 ): N it ≈ cm krad  N it ≈2·10 11 cm krad  N it ≈7·10 11 cm -2 No change in the transconductance g m

Discussion of the results Comparison of N ox and N it between MOS-C and gated diode for Al- and poly-gate structure at dose of 189krad and 1Mrad For N ox : a good agreement for poly-gate structure (MOS-C & gated diode) For Al-gate structure: more N it and N ox on MOS-C than on Gated diode More N it and N ox for Al-gate than poly-gate structure (MOS-C) For N ox : the same for both Al-gate and poly- gate structure (Gated diode) doseN ox MOS-CGated diode 189kradAl8,3e113,3e11 189kradPoly3,3e112,6e11 doseN it MOS-CGated diode 189kradAl2,8e115,1e10 189kradPoly6e101,2e11 doseN ox MOS-CGated diode 1MradAl1,9e125,7e11 1MradPoly6,7e115,7e11 doseN it MOS-CGated diode 1MradAl6,8e111,2e11 1MradPoly1,1e112,1e11 For poly-gate structure: more N it on Gated diode than on MOS-C For N ox : More N it for poly-gate than Al-gate structure (Gated diode) doseDEPFETN ox N it 912kradPoly6~7e117e11 For N ox : DEPFET=Gated diode MOS-C √ For N it : DEPFET>Gated diode>MOS-C ? (Poly-gate structure for three devices) ≈ ≈ ≈ ≈

Comparison between literature and our experiment Differences for the saturation effect of interface trap on MOS-C Differences for the generation of defects on MOS-C (poly-gate for DEPFET) Differences for defect generation at negative gate bias on MOS-C T.P. Ma, P. Dressendorfer John Wiley&Sons,1989. Winokur, Derbenwick, Gregory, 1975

Backup slides

Performance before irradiation 55 Fe Energy (eV) Counts/channel o non-irrad. double pixel DEPFET o L=7μm, W=25 μm o V thresh ≈-0.2V, V gate =-1V o I drain =41 μA o Drain current read out o time cont. shaping  =6 μs Noise ENC=2.3 e - (rms) at T>23 degC

Non-irradiated: Noise ENC=2.3 e - (rms) Performance after irradiation for DEPFET 55 Fe Energy (eV) Counts/channel o Irradiated double pixel DEPFET o L=7μm, W=25 μm o after 913 krad, 60 Co o V thresh ≈-4V, V gate =-5.3V o I drain =21 μA o Drain current read out o time cont. shaping  =6 μs Noise ENC=7.9 e - (rms) at T>23 degC