Readout Architecture for MuCh Introduction of MuCh Layout of Much ( proposed several schemes) Read ASIC’s Key features Basic Readout chain ROC Block Diagram Requirements to desig the FEB Conceptual sketch of Tripple GEM Chamber with FEB Indian contribution to CBM MuCh Electronics

muon system consists of 16 detector layers with 100 μm position resolution 5 absorber layers made of tungsten, iron and carbon of variable thickness. The structure : one sensitive layer is in front of the first absorber, three sensitive layers are between each two absorbers and three behind last absorber. 2 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009 Introduction

Several schemes for MuCh are proposed :  Modular Square Chamber  Slat type  Sector type ( 8Sectors) 2m 300 mm Chambers layout for MuCh Modular Square Chamber  One module is 30cm x 30cm  36 Nos. of Modules in one plane  Profile is more to reduce dead space 3 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Slat Type 2m  20 Chambers  Width of each chamber 10 cm. X-section of chamber  Profile is less as compared to modular design  Wastage of chamber space Chambers layout for MuCh 4 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Sector Type  8 Nos. of Sectors  No wastage of chamber Space  Similar type of chamber  Less profile 5 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Read-out ASIC to be used for MuCh is n-XYTER / CBM-XYTER  mixed signal chip  process: AMS 0.35 μm CMOS  128 channels  1 test channel with analogue diagnostic output  architecture for AC-coupling, employable for positive and negative signals  self triggered, data driven de-randomizing, sparcifying readout at 32 MHz  digital time stamp output  analogue peak hight output  maximum data loss at 32 MHz average input rate over 16 μs: 4% Key Features 6 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

analogue pile-up registry programmable dead time local threshold adjustment Dynamic Range: e Shaping time and noise performance: 30 ns fast shaper at 30 pF input, 850 enc for positive signals, 1000 enc for negative signals 130 ns slow shaper at 30 pF input, 600 enc Timing resolution ~ 2-3 ns, time stamp resolution 1 ns Key Features contd..

Basic n-XYTER Readout Chain Detector FEBROC XYTER ADC XYTER Tag data ADC data clock FPGA control SFP MGT DCB FPGA SFP MGT Front-End Board Read-Out Controller Data Combiner Board to other ROC's to ABB SFP MGT 8 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009 From Walter F.J. Mueller’s lecture

PC Some Configurations Detector FEBROCABB PC DCBABB Detector FEBROC Detector FEBROC Detector FEBROC Detector FEBROC Minimal Configuration Expandable Configuration 95th CBM-India Collaboraton Meeting, BHU, S. K. Pal29/12/2009

Block Diagram of ROC Board  Two nos. of such Boards are already fabricated in India  Functional testing is in progress  Details in M.S.Dey’s lecture Diagram taken from CBM-Wiki page 10 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 11 Input needed to design the FEB  Type of package of XYTER chip  No. of Channels in one XYTER chip ( 64 or 128 or 32 ?)  Pad Size of the Detector  Gap between chamber and absorber i.e maximum available profile for FEB  Radiation dose on the Detector en d. Things to be considered at the Detector end:  Cooling of the FEB  Power ( LV ) connection to FEBs  Connectivity between FEB and ROC … and many more …

Gas out Gas in HV (9 segments ) 300 mm Conceptual sketch of Triple GEM chamber module 256ch. FEB 36 FEBs=9216chs 12 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

3-GEM chamber Heat sink XYTER 256 ch- FEB chamber frame X-section of chamber 13 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Profile of Chamber 3GEM Chamber 50mm Heat Sink XYTER chip FEB PCB Chamber PCB Connector 10mm 14 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Tracking station plane 2m ROC stack 15 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009

Indian Contribution to CBM MUCH Electronics India could supply complete detector system with electronics! XYTER integration for 0.5x10 6 detector channels: 2-chips or 4-chips (256 channels) to one hybrid FEE pcb (estimated 2000 boards) FPGA-based readout controller (ROC) adaptation and assembly ( ~500 boards needed) For a test case 2 ROC boards of current version have already been fabricated in India The cost factor is the integration of chips !! 16 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 29/12/2009