1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp

ISPD'032 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'033 Process Variation T S W H Ground plane t ox Junction depth Gate width Gate length Etching errors Mask misalignment Spot defects

ISPD'034 Impact to Clock Skew 20-30% variation on clock skew, mostly due to clock buffers ( Zanella, et al., TCAD 12/2000 ) Interconnect variations may cause up to 25% variation on clock skew ( Y. Liu, et al., DAC 2000 ) Undesired skew  bottleneck of clock frequency

ISPD'035 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'036 Previous Work Buffer insertion/sizing [Chung and Cheng, ICCAD 94] [Xi and Dai, DAC 95] Wire sizing [Pullela, Menezes and Pillage, DAC 93] Non-tree topology [Lin and Wong, ICCAD 94] [Su and Sapatneker, ICCAD 01] Abstract topology [Velenis, Friedman and Papaefthymiou, ISCAS 01]

ISPD'037 Focus on Clock Tree Routing Interconnect variation is significantly important Unlike transistors, worst case skew from interconnect variation is not at corner points Result can be applied as a sub-network in buffered/non-tree clock network

ISPD'038 Wire Width Variation Model -3  -2  -1  +1  +2  +3  WsWs 68.26% 95.44% 99.74% WuWu WlWl Wire width: w = W s +  W s = W 0 + x +  y Lower limit: W l = W s - 3  Upper limit: W u = W s + 3   : standard deviation =  = 3   d max d max max dist between sinks

ISPD'039 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'0310 Problem Formulation Permissible range for sink s i and s j [ LPR ij, UPR ij ] Skew violation max ( LPR ij – skew ij, skew ij – UPR ij ) Minimizing Skew Violation ( MinSV ): Given a set of clock sinks { s 1, s 2, …, s n }, skew permissible ranges for all pairs of sinks, [ W l, W u ], find a clock routing tree such that the max skew violation among all sink pairs is minimized

ISPD'0311 Assumptions Elmore delay model Given abstract topology

ISPD'0312 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'0313 DME Based Framework Deferred Merge Embedding (DME) –Bottom-up, find merging segments –Top-down, find locations for internal nodes

ISPD'0314 Find Merging Locations For particular z value –Skew range [ skew ij, min, skew ij, max ] z , range shifts to greater values z , range shifts to smaller values Adjust z such that center of skew range is aligned to center of permissible range In DME, adjust z such that skew ij = 0 sisi sjsj nini njnj n z D ij

ISPD'0315 Align Skew Range sisi sjsj nini njnj n z D ij Permissible range Skew range z = 0 Skew range z = D ij

ISPD'0316 When Snaking Necessary sisi sjsj nini njnj n D ij Permissible range Skew range z = 0 Skew range z = D ij Permissible range Skew range z = 0 Skew range z = D ij sisi sjsj nini njnj n D ij

ISPD'0317 Worst Case Skew Estimation skew ij,min = t i,min – t j,max skew ij,max = t i,max – t j,min Need to estimate min and max delay to a sink under process variation

ISPD'0318 Worst Case Delay Estimation: Single Sink Wire capacitance clw Wire resistance rl/w t = rcl 2 /2 + rl C/w t min = rcl 2 /2 + rl C/W U t max = rcl 2 /2 + rl C/W L l C w

ISPD'0319 Worst Case Delay Estimation: Multiple Sinks t pi,min –Width of path n p -> s i is W U –Width of wires not on n p ->s i is W L t pi,max –Width of path n p -> s i is W L –Width of wires not on n p ->s i is W U sisi sjsj sksk npnp

ISPD'0320 How to Choose Sink Pair How to choose s i in left subtree and s j in right subtree? Ideally, need to evaluate all sink pairs between left and right subtree –Greatly increase computation cost Heuristic: pick the most critical pair Criticality ij = d ij  d max + PR min  PR ij d max : max sink pair distance PR min : min permissible range sisi sjsj nini njnj n

ISPD'0321 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'0322 Experiments Benchmark circuits r1-r5 SUN Blade-100 workstation, 512M memory Compare with extended DME –Align nominal skew to center of permissible range S: permissible range LPR, UPR symmetric wrt 0 NS: LPR, UPR asymmetric wrt 0

ISPD'0323 Number of Skew Violations

ISPD'0324 Maximum Skew Violation

ISPD'0325 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'0326 Pair-wise Bounded Skew Routing Minimizing Wirelength s.t. Skew Constraints: Given a set of clock sinks { s 1, s 2, …, s n }, skew permissible ranges for all pairs of sinks, find a clock routing tree such that the total wirelength is minimized while all permissible range are satisfied Find merging regions instead of merging segments Similar to Bounded Skew Clock Routing [Cong, et al., ACM TODAES 98] Pair-wise skew permissible range vs. global skew bound More wirelength reduction

ISPD'0327 Outline Introduction Previous work Problem formulation Minimum skew violation clock tree Experimental results Extension to bounded skew clock tree Conclusion

ISPD'0328 Conclusion Wire width variation needs to be considered in clock tree routing Worst delay variation can be estimated given the wire width variation range Our MinSV method significantly improves tolerance to wire width variation Our method can be extended to pair-wise bounded skew routing to further reduce the total wire length

ISPD'0329 Thank you!