Multi-Mode Trace Signal Selection for Post-Silicon Debug Min Li and Azadeh Davoodi Department of Electrical and Computer Engineering University of Wisconsin-Madison.

Slides:



Advertisements
Similar presentations
Overcoming Limitations of Sampling for Agrregation Queries Surajit ChaudhuriMicrosoft Research Gautam DasMicrosoft Research Mayur DatarStanford University.
Advertisements

Presenter : Shih-Tung Huang 2015/4/30 EICE team Automated Data Analysis Solutions to Silicon Debug Yu-Shen Yang Dept. of ECE University of Toronto Toronto,
1 of 14 1 /23 Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems Paul Pop, Petru Eles, Zebo Peng Department of Computer and Information.
Reap What You Sow: Spare Cells for Post-Silicon Metal Fix Kai-hui Chang, Igor L. Markov and Valeria Bertacco ISPD’08, Pages
BackSpace: Formal Analysis for Post-Silicon Debug Flavio M. de Paula * Marcel Gort *, Alan J. Hu *, Steve Wilton *, Jin Yang + * University of British.
Reachability Analysis for AMS Verification using Hybrid Support Function and SMT- based Method Honghuang Lin, Peng Li Dept. of ECE, Texas A&M University.
Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation Vishal Khandelwal and Ankur Srivastava Department of.
Variability in Architectural Simulations of Multi-threaded Workloads Alaa R. Alameldeen and David A. Wood University of Wisconsin-Madison
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum & Minerals.
Date:2011/06/08 吳昕澧 BOA: The Bayesian Optimization Algorithm.
Active Calibration of Cameras: Theory and Implementation Anup Basu Sung Huh CPSC 643 Individual Presentation II March 4 th,
Presenter : Shao-Jay Hou. Today’s complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon.
Dec. 19, 2005ATS05: Agrawal and Doshi1 Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849,
Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.
Presenter: Shao-Jay Hou. Embedded logic analysis has emerged as a powerful technique for identifying functional bugs during post- silicon validation,
Reporter : Mac Date : Multi-Start Method Rafael Marti.
Scheduling with Optimized Communication for Time-Triggered Embedded Systems Slide 1 Scheduling with Optimized Communication for Time-Triggered Embedded.
Efficient Reachability Checking using Sequential SAT G. Parthasarathy, M. K. Iyer, K.-T.Cheng, Li. C. Wang Department of ECE University of California –
Jan 6-10th, 2007VLSI Design A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.
Feature Screening Concept: A greedy feature selection method. Rank features and discard those whose ranking criterions are below the threshold. Problem:
Jieyi Long and Seda Ogrenci Memik Dept. of EECS, Northwestern Univ. Jieyi Long and Seda Ogrenci Memik Dept. of EECS, Northwestern Univ. Automated Design.
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
Principle of Functional Verification Chapter 1~3 Presenter : Fu-Ching Yang.
WISCAD – VLSI Design Automation GRIP: Scalable 3-D Global Routing using Integer Programming Tai-Hsuan Wu, Azadeh Davoodi Department of Electrical and Computer.
L i a b l eh kC o m p u t i n gL a b o r a t o r y Trace-Based Post-Silicon Validation for VLSI Circuits Xiao Liu Department of Computer Science and Engineering.
Efficient Model Selection for Support Vector Machines
Accuracy-Configurable Adder for Approximate Arithmetic Designs
A Parallel Integer Programming Approach to Global Routing Tai-Hsuan Wu, Azadeh Davoodi Department of Electrical and Computer Engineering Jeffrey Linderoth.
Power Reduction for FPGA using Multiple Vdd/Vth
Confidentiality Preserving Integer Programming for Global Routing Hamid Shojaei, Azadeh Davoodi, Parmesh Ramanathan Department of Electrical and Computer.
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock Sindhu Gunasekar Vishwani D. Agrawal.
An Iterative Heuristic for State Justification in Sequential Automatic Test Pattern Generation Aiman H. El-MalehSadiq M. SaitSyed Z. Shazli Department.
Reporter :PCLee The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed.
Euro-Par, A Resource Allocation Approach for Supporting Time-Critical Applications in Grid Environments Qian Zhu and Gagan Agrawal Department of.
Statistical Sampling-Based Parametric Analysis of Power Grids Dr. Peng Li Presented by Xueqian Zhao EE5970 Seminar.
A Power Grid Analysis and Verification Tool Based on a Statistical Prediction Engine M.K. Tsiampas, D. Bountas, P. Merakos, N.E. Evmorfopoulos, S. Bantas.
1 Hybrid-Formal Coverage Convergence Dan Benua Synopsys Verification Group January 18, 2010.
A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design
Preeti Ranjan Panda, Anant Vishnoi, and M. Balakrishnan Proceedings of the IEEE 18th VLSI System on Chip Conference (VLSI-SoC 2010) Sept Presenter:
Ground Truth Free Evaluation of Segment Based Maps Rolf Lakaemper Temple University, Philadelphia,PA,USA.
Design of a High-Throughput Low-Power IS95 Viterbi Decoder Xun Liu Marios C. Papaefthymiou Advanced Computer Architecture Laboratory Electrical Engineering.
VTS 2012: Zhao-Agrawal1 Net Diagnosis using Stuck-at and Transition Fault Models Lixing Zhao* Vishwani D. Agrawal Department of Electrical and Computer.
Feng-Xiang Huang Test Symposium(ETS), th IEEE European Ko, Ho Fai; Nicolici, Nicola; Department of Electrical and Computer Engineering,
A Stable Fixed-outline Floorplanning Method Song Chen and Takeshi Yoshimura Graduate School of IPS, Waseda University March, 2007.
MINING COLOSSAL FREQUENT PATTERNS BY CORE PATTERN FUSION FEIDA ZHU, XIFENG YAN, JIAWEI HAN, PHILIP S. YU, HONG CHENG ICDE07 Advisor: Koh JiaLing Speaker:
Sparse Signals Reconstruction Via Adaptive Iterative Greedy Algorithm Ahmed Aziz, Ahmed Salim, Walid Osamy Presenter : 張庭豪 International Journal of Computer.
Jing Ye 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences.
Min Li and Azadeh Davoodi
A local search algorithm with repair procedure for the Roadef 2010 challenge Lauri Ahlroth, André Schumacher, Henri Tokola
1 Twin Binary Sequences: A Non-Redundant Representation for General Non-Slicing Floorplan Evan Young Department of Computer Science and Engineering The.
VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India Few Good Frequencies for Power-Constrained Test Sindhu Gunasekar and Vishwani D.
Virtual Examples for Text Classification with Support Vector Machines Manabu Sassano Proceedings of the 2003 Conference on Emprical Methods in Natural.
TFA: A Tunable Finite Automaton for Regular Expression Matching Author: Yang Xu, Junchen Jiang, Rihua Wei, Yang Song and H. Jonathan Chao Publisher: ACM/IEEE.
International Symposium on Physical Design San Diego, CA April 2002ER UCLA UCLA 1 Routability Driven White Space Allocation for Fixed-Die Standard-Cell.
Congestion Analysis for Global Routing via Integer Programming Hamid Shojaei, Azadeh Davoodi, and Jeffrey Linderoth* Department of Electrical and Computer.
-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,
-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.
SEMI-SYNTHETIC CIRCUIT GENERATION FOR TESTING INCREMENTAL PLACE AND ROUTE TOOLS David GrantGuy Lemieux University of British Columbia Vancouver, BC.
Fast Synthesis of Clock Gating from Existing Logic Aaron P. Hurst Univ. of California, Berkeley Portions In Collaboration with… Artur Quiring and Andreas.
Gill 1 MAPLD 2005/234 Analysis and Reduction Soft Delay Errors in CMOS Circuits Balkaran Gill, Chris Papachristou, and Francis Wolff Department of Electrical.
Trace Signal Selection for Post-Silicon Debug W ISCAD Electronic Design Automation Lab
On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University.
Unified Adaptivity Optimization of Clock and Logic Signals Shiyan Hu and Jiang Hu Dept of Electrical and Computer Engineering Texas A&M University.
Prediction of Interconnect Net-Degree Distribution Based on Rent’s Rule Tao Wan and Malgorzata Chrzanowska- Jeske Department of Electrical and Computer.
High-Speed Stochastic Circuits Using Synchronous Analog Pulses M
Standard-Cell Mapping Revisited
Fast Computation of Symmetries in Boolean Functions Alan Mishchenko
Aiman H. El-Maleh Sadiq M. Sait Syed Z. Shazli
Improved Design Debugging using Maximum Satisfiability
Presentation transcript:

Multi-Mode Trace Signal Selection for Post-Silicon Debug Min Li and Azadeh Davoodi Department of Electrical and Computer Engineering University of Wisconsin-Madison W ISCAD Electronic Design Automation Lab

2 Outline Preliminaries –Overview of post-silicon debug (PSD) using trace buffers –Review of restoration process and previous works Introduction to restoration using control signals and operation modes Motivation of multi-mode trace selection (MMTS) An iterative MMTS algorithm –New metrics for trace signal selection –Mode merging and iterative selection process Experimental results

3 Post-Silicon Debug Real-time operation of a few manufactured chips with real-world stimulus Involves finding errors causing malfunctions –Fix through multiple rounds of Silicon Stepping/Revision Has become significantly time- consuming and expensive –Tight Time-to-Market requirement –Formal verification and simulation tools do not scale as technology scales –Poor visibility inside the chip

4 Use trace buffer technology 1.Trigger an event in the CUD 2.Real-time capture traces on a few selected state elements through on-chip buffer 3.Extract and analyze Reveals internal states at real-time operation Off-chip state restoration [Figure from Yang, et al DATE09] Debug using Trace Buffers

5 Trace Signal Selection Problem Limitation –Small trace buffer width (8~32 bits) and depth (1K~8K clock cycles) –Limited on-chip white spaces Automated trace selection –Need to select a subset of state elements to trace such that the visibility of internal signals is maximized –Based on algorithms rather than hints and experiences

6 Restoration Using Traced Signals Forward Propagation Backward Justification f1f1 f2f2 f4f4 f5f5 f3f DFF\Cycle01234 F1XXXXX F20110X F3XXXXX F4XXXXX F5XXXXX 110XX X11XX X0XX0 State Restoration Ratio (SRR): # tot. FF restored # tot. FF traced e.g. in this example 11/4=2.75

7 Control Signals and Modes f1f1 f3f3 f2f2 c control signal

8 Need to Consider Multiple Modes Case study of S38584 –For each solution evaluated the SRR for mode 0 and 1 –Ran single mode trace selection (SMTS) procedure (of Li & Davoodi [DATE’13]) twice, for modes 0 and 1, to select two different sets of trace signals –For each solution evaluated the SRR for mode 0 and 1

9 Previous Works Previous works give procedures for solving the trace selection problem for a single operation mode ‒ Ko & Nicolici [DATE’08] ‒ Liu & Xu [DATE’09] ‒ Prabhakar & Xiao [ATS’09] ‒ Basu & Mishra [VLSI’11] ‒ D. Chatterjee [ICCAD’11]: pure simulation with backward elimination ‒ Li & Davoodi [DATE’13]: a hybrid algorithm combining fast metric and accurate simulation Two major drawbacks of applying single mode trace selection algorithms for multi-modes ‒ Traces selected for different modes may have little in common ‒ Traces selected for one mode may not be good for other modes

10 Contributions A new metric and problem definition when considering multiple modes –Multi-mode State Restoration Ratio (MSRR) –Multi-Mode Trace Selection problem (MMTS) Algorithms for solving MMTS including –A procedure to reduce the number of modes by merging the modes with “similar” restoration maps –A procedure based on perturbing an initial single-mode optimized solution (selected from a suitable “start” mode) to improve the restorability over all the modes

11 Multi-mode Trace Selection Problem

12 Mode Merging: Motivation For S35932 we plotted four restoration maps when each of its four operation modes are set to the corresponding values (when no trace signal is selected yet) In each restoration map –Green pixel: gate restored to 0 –Black pixel: gate restored to 1 –Red pixel: unrestored gate Observations –Modes with similar restoration maps can be merged into a single mode –In this case, modes 0 and 1 can be merged, so is modes 2 and 3c

13 Mode Merging: Procedure Y N Merged the two modes (into one of the modes) Can’t merge the two modes

14 MMTS Procedure: Metrics f1f1 f3f3 f2f2 c

15 MMTS Procedure: Metrics

16 MMTS Procedure: Metrics

17 IteM: Iterative Multi-mode Trace Selection Overview of our procedure: 1.Identify a suitable start mode m init –For each mode compute a set representing the union of the reachability lists for all the flipflops in that mode, and then let the start mode to be the one which has the highest size for this set 2.Find an initial solution to maximize the SRR in mode m init ‒ Generated using Li & Davoodi [DATE’13] 3.Iteratively perturb the current solution for better multi-mode restoration –Has a a non-greedy nature –Is based on a gradually-increasing perturbation radius r within each iteration –Specifically, at each iteration, up to R=3 number of trace signals in the current solution may be swapped 4.The process terminates upon observing no improvements in MSSR in 20 consecutive iterations

18 IteM: Iterative Multi-mode Trace Selection Swap r signals r > R ? DONE Set swap to DET (deterministic); radius r=1 START Swap is DET ? Set swap to RAND (random); radius r=1 Accept ? r++ N N Y Y N Y swap RAND r=1 signal Overview of swap for R trace signals: Gradually increases the perturbation radius from r=1 to r=R Uses a probabilistic acceptance criteria similar to simulated annealing to probabilistically accept the swaps when there is no improvement in MSRR

19 IteM: Iterative Multi-mode Trace Selection

20 Experimental Results Bench#FF#GatesMSuite S ISCAS89 S ISCAS89 b IWLS05 b IWLS05 dsp IWLS05 DMA ISPD12 des_perf ISPD12 All benchmarks (excluding S38584 and S35932) are much larger compared to the ISCAS’89 used in prior works dsp has the maximum reduction in the number of modes, from 8 to 2, due to mode merging Benchmark Information

21 Implemented Approaches RATS: implemented the single-mode procedure of Basu & Mishra [VLSI’11] HYBR: single-mode procedure of Li & Davoodi [DATE’13] (our previous work) SimF: single-mode forward-greedy selection based on simulation HYBRM: simple extension of HYBR for multi-mode signal selection IteM: the proposed iterative multi-mode selection procedure (this work) REF: upper bound computed by adding the highest attainable SRR per mode –Highest SRR/mode computed by solving the single-mode trace selection in that mode using various algorithms

22 Comparison of MSRR BenchREFRATSHYBRSimFHYBRMIteM S S b N/A b N/A dsp 42.80N/A DMA des_perf 77.60N/A Average 1.00N/A REF column reports MSRR and the remaining columns are normalized with respect to REF Observations: IteM consistently performs better than other methods

23 Comparison of Runtime BenchRATSHYBRSimFHYBRMIteM S S b17 < 24hrs b18 < 24hrs dsp < 24hrs DMA des_perf < 24hrs Runtime is reported in minutes –RATS, although fast for the ISCAS89 benchmarks, didn’t scale for the large benchmarks (took more than 24hrs) The runtime of IteM is reasonable given the large size of the benches and comparable with HYBRM which is based on simple extension of the very fast HYBR

24 Conclusions We proposed the multi-mode trace signal selection problem (MMTS) We introduced a strategy to merge the modes with similar restoration maps We proposed an algorithm to solve the problem based on iterative perturbation of an initial solution obtained from a single but suitable start mode Experimental results showed that the iterative algorithm performs better than various single-mode or multi-mode algorithms, with a high solution quality comparable to the reference case

25 References 1)K. Basu and P. Mishra. RATS: restoration-aware trace signal selection for post-silicon validation. In IEEE TVLSI, )D. Chatterjee, C. McCarter, and V. Bertacco. Simulation-based signal selection for state restoration in silicon debug. In ICCAD, )M. Li and A. Davoodi. A hybrid approach for fast and accurate trace signal selection for post-silicon debug. In DATE, )H. F. Ko and N. Nicolici. Algorithms for state restoration and trace signal selection for data acquisition in silicon debug. In IEEE Trans. On CAD, )X. Liu and Q. Xu. On signal selection for visibility enhancement in trace-based post-silicon validation. In IEEE Trans. on CAD, 2012

Thank You!

27 Experimental Results W Merge W/O Merge Comparison of Merged/Unmerged Cases Apply the iterative algorithm on the three benches having mode reduction (merged) For “W Merge” case, randomly pick one mode to represent the modes merged For MSRR comparison, raw numbers are shown (without normalization). For runtime comparison, results of the “W/O Merge” case are normalized to “W Merge” Mode merging can significantly reduce the runtime while obtaining a comparable solution quality