Basic Memory Management Chapter 3 C6000 Integration Workshop Copyright © 2005 Texas Instruments. All rights reserved. Technical Training Organization T TO

Outline  C6416 Memory Architecture  C6713 Memory Architecture  Section  Memory Placement Technical Training Organization T TO

'C6416 Internal Memory 0000_0000 Level 2 Internal Memory   Level 1 Memory   Always cache ( not in map )   L1P (prog), L1D (data)   Level 2 Memory (L2)   RAM (prog or data)   Up to 256 KB can be cache C6416 L1P=16 KB L1D=16 KB L2=1 MB C6416 L1P=16 KB L1D=16 KB L2=1 MB FFFF_FFFF L2 RAM Prog/Data CPU EMIF A EMIF B Program Cache Data Cache Technical Training Organization T TO

C64x External Memory 0000_0000 Level 2 Internal Memory External (A2) External (A3) A000_0000 B000_0000 FFFF_FFFF External (A0) External (A1) 8000_ _0000 External (B2) External (B3) 6800_0000 6C00_0000 External (B0) External (B1) 6000_ _0000 L2 RAM Prog/Data CPU EMIF A EMIF B C64x memory details... Program Cache Data Cache   Each EMIF has four ranges   Program or Data   Named: CE0, CE1, CE2, CE3   Remaining memory is unused

C64x Memory Details 0000_0000 Level 2 Internal Memory External (A2) External (A3) A000_0000 B000_0000 FFFF_FFFF External (A0) External (A1) 8000_ _0000 External (B2) External (B3) 6800_0000 6C00_0000 External (B0) External (B1) 6000_ _0000 DevicesInternal (L2) External C6414 C6415 C6416 1MB A:1GB (64-bit) B:256MB (16-bit) DM642256KB 1GB (64-bit) C KB 256MB (32-bit)   Each device is different   Some have two EMIF's   EMIFA is 64-bits wide   EMIFB is 16-bits wide

'C6416 DSK Block Diagram Daughter-Card Room for Expansion SDRAM (16MB) CE2 CE3 Flash ROM (512KB) CPLD CE1 CE0   DSK uses both EMIFs (A and B)   EMIFA   CE0 for SDRAM   CE2 and CE3 pinned-out to daughter card connector   EMIFB   CE1 for Flash Memory and CPLD (switches, LED’s, etc.) L2 RAM Prog/Data (1MB) CPU EMIF A EMIF B Program Cache Data Cache CE0

What is a Memory Map? 1 GB 8000_0000 CE0 A000_0000 CE2 C6000 CPU SRAM EMIF B000_0000 CE3 9000_0000 CE1 1 GB A Memory Map is a table representation of memory… 8000_ _0000 B000_0000 A000_ _0000 1GB CE3 1GB CE2 1GB CE1 1GBCE0 1MB L2 SRAM Technical Training Organization T TO

C6416 DSK Memory Map CPLD:   LED’s   DIP Switches   DSK status   DSK rev#   Daughter Card 0000_0000 Internal RAM: 1MB 0010_0000 Internal Peripherals or reserved 6000_0000 EMIFB CE0 : 64MB CPLD 6400_0000 EMIFB CE1 : 64MB Flash: 512KB 6800_0000 EMIFB CE2 : 64MB 6C00_0000 EMIFB CE3 : 64MB 8000_0000 EMIFA CE0 : 256MB SDRAM: 16MB 9000_0000 EMIFA CE1 : 256MB A000_0000 EMIFA CE2 : 256MB Daughter Card B000_0000 EMIFA CE3 : 256MB TMS320C6416C6416 DSK Technical Training Organization T TO

Outline C6416 Memory Architecture  C6713 Memory Architecture  Section  Memory Placement Technical Training Organization T TO

'C6713 Internal Memory 0000_0000 Level 2 Internal Memory   Level 1 Memory   Always cache ( not in map )   L1P (prog), L1D (data)   Level 2 Memory (L2)   192KB RAM (prog or data)   Up to 64KB cache L2 SRAM prog/data CPU Program Cache Data Cache C6713 L1P=4 KB L1D= 4 KB L2=256 KB C6713 L1P=4 KB L1D= 4 KB L2=256 KB FFFF_FFFF EMIF What about the External Memory? Technical Training Organization T TO

'C6713 External Memory 0000_0000 Level 2 Internal Memory FFFF_FFFF Level 2 Prog/Data CPU Program Cache Data Cache External (CE2) External (CE3) A000_0000 B000_0000 External (CE0) External (CE1) 8000_ _0000 EMIF   Four External ranges   Program or Data   128 Mbytes each   Named: CE0, CE1, CE2, CE3   Remaining memory is unused How does this apply to the DSK? Technical Training Organization T TO

'C6713 DSK Block Diagram Daughter-Card Room for Expansion Internal Memory CPU Program Cache Data Cache EMIF SDRAM (16MB) CE2 CE3 Flash ROM (256KB) I/O Port CE1 CE0   DSK uses all four External Memory regions   CE0 for SDRAM   CE1 for Flash Memory and I/O Port (switches, LED’s, etc.)   CE2 and CE3 pinned-out to daugher card connector So what does the Memory Map look like?

FFFF_FFFF 0000_ KB Internal Program / Data Peripheral Regs 0180_ MB External 8000_ _0000 A000_0000 B000_ MB External TMS320C6713 Available via Daughter Card Connector ‘C6713 DSK 16MB SDRAM 256K byte FLASH CPLD C6713 DSK Memory Map CPLD:   LED’s   DIP Switches   DSK status   DSK rev#   Daughter Card 9008_0000

Outline C6416 Memory Architecture C6713 Memory Architecture  Section  Memory Placement Technical Training Organization T TO

Sections short m = 10; short x = 2; short b = 5; main() { short y = 0; y = m * x; y = y + b; printf("y=%d",y); }   Every C program consists of different parts called Sections   All default section names begin with "." Let’s review the list of compiler sections… Global Vars (.bss)Init Vals (.cinit) Local Vars (.stack) Code (.text) Std C I/O (.cio) Technical Training Organization T TO

Software System Initialization Sections.hwi_vec.sysinit Where would you place these two sections?.hwi_vecEPROM.sysinitEPROM Config Tool and Compiler handle reset and system init for you Reset Vector reset pin Software System Initialization _c_int00 short m = 10; short b = 2; short x = 5; main() { short y = 0; y = m * x; y = y + b; printf("y=%d",y); } short m = 10; short b = 2; short x = 5; main() { short y = 0; y = m * x; y = y + b; printf("y=%d",y); } Technical Training Organization T TO

Compiler's Section Names Section Name Description Memory Type.textCodeinitialized.switchTables for switch instructionsinitialized.constGlobal and static string literalsinitialized.cinitInitial values for global/static varsinitialized.pinitInitial values for C++ constructorsinitialized.bssGlobal and static variablesuninitialized.farGlobal and static variablesuninitialized.stackStack (local variables)uninitialized.sysmemMemory for malloc fcns (heap)uninitialized.cioBuffers for stdio functionsuninitialized Technical Training Organization T TO

Exercise 16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Where would you place each of these sections? SectionLocationWhy.text.cinit.bss.stack.cio

16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Solution Where would you place each of these sections? SectionLocationWhy.textFLASHMust exist after reset.cinit.bss.stack.cio Initialized Memory

16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Solution Where would you place each of these sections? SectionLocationWhy.textFLASHMust exist after reset.cinitFLASHMust exist after reset.bss.stack.cio Initialized Memory

16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Solution Where would you place each of these sections? SectionLocationWhy.textFLASHMust exist after reset.cinitFLASHMust exist after reset.bssInternalMust be in RAM memory.stack.cio Initialized Memory

16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Solution Where would you place each of these sections? SectionLocationWhy.textFLASHMust exist after reset.cinitFLASHMust exist after reset.bssInternalMust be in RAM memory.stackInternalMust be in RAM memory.cio Initialized Memory

16MB SDRAM 8000_0000 CE0 4MB FLASH 9000_0000 CE1 C6000 CPU Internal Memory Solution Where would you place each of these sections? SectionLocationWhy.textFLASHMust exist after reset.cinitFLASHMust exist after reset.bssInternalMust be in RAM memory.stackInternalMust be in RAM memory.cioSDRAM Needs RAM, speed not critical Initialized Memory Technical Training Organization T TO

Placing Sections In Memory.text.bss.cinit.cio.stack   How do you define the memory areas (e.g. FLASH, SDRAM) ?   How do you place the sections into these memory areas ? 8000_ _0000 4MB FLASH 16MB SDRAM 1MB Internal 0000_0000 Technical Training Organization T TO

Using the Memory Section Manager   MEM Manager allows you to create memory areas & place sections   To Create a New Memory Area:   Right-click on MEM and select Insert Mem   Fill in base/len, etc. How do you place sections into these memory areas? Technical Training Organization T TO

MEM Manager Properties   To Place a Section Into a Memory Area… Right-click on MEM Section Manager and select Properties Select the appropriate tab (e.g. Compiler) Select the memory area for each section What about the BIOS Sections? Technical Training Organization T TO

Placing BIOS Sections   BIOS creates both Data and Code sections   User needs to place these into appropriate memory region What gets created after you make these selections? Technical Training Organization T TO

Initialized Memory CPU IRAM.out file.bios.sysinit.gblinit.trcdata.hwi_vec.rtdx_text.text.switch.cinit.pinit.const   CCS loader copies the following sections into volatile memory: Technical Training Organization T TO

Config Tool Creates CDB File *cfg_c.c *cfg.s62 *cfg.cmd *cfg.h *cfg.h62   Config tool generates five different files   Notice, one of them is the linker command file   CMD file is generated from your MEM settings MEMORY{ EPROM: origin=0, length = 0x20000 … } SECTIONS {.text: > EPROM.cinit:> EPROM.bss: > IDRAM … } MEMORY{ EPROM: origin=0, length = 0x20000 … } SECTIONS {.text: > EPROM.cinit:> EPROM.bss: > IDRAM … } Technical Training Organization T TO

GUI’s Linker Command File app.cdb Linker appcfg.cmd myApp.out   Do not modify appcfg.cmd – your changes will be overwritten during “Build” (or “Rebuild”) “Build”.obj files libraries (.lib).map Technical Training Organization T TO

Outline C6416 Memory Architecture C6713 Memory Architecture Section  Memory Placement Technical Training Organization T TO

Lab 3 – Using the Map File Use.cdb file to move sections in memory and check results with map file   Goal   Move Buffers to SDRAM   Read Map File   Procedure c6xxx.CDB Technical Training Organization T TO

 Go directly to Chapter 4 Optional Topics  ’0x Memory Scheme  C6201, C6202, C6203, C6204, C6205  C6701  ‘1x Memory Scheme  C6211  C6711, C6712, (C6713)  (C6411), C6414, C6415, C6416 Technical Training Organization T TO

'0x Memory Scheme 16 MB 0000_0000 CE0 4 MB 0100_0000 CE1 16 MB 0200_0000 CE2 16 MB 0300_0000 CE3 C6000 CPU 0140_0000 Program EMIF 8000_0000 Data This block diagram represents the maximum allowable memory for the 'C6x0x devices … Technical Training Organization T TO

'0x Memory Scheme 16 MB 0000_0000 CE0 4 MB 0100_0000 CE1 16 MB 0200_0000 CE2 16 MB 0300_0000 CE3 C6000 CPU 0140_0000 Program EMIF 8000_0000 Data 0000_ MB External (CE0) External (CE1) Internal Program 0100_ _0000 CE0 CE1   A Memory Map is a table representation of memory   This is more convenient than a block diagram description Technical Training Organization T TO

'0x Memory Scheme 0000_0000 Internal Program 0100_ _ MB External (CE0) CE0 4MB External (CE1) CE1 Internal Data 16MB External (CE0) CE2 16MB External (CE0) CE3 0200_ _ _0000 FFFF_FFFF   All '0x devices share same external memory map   CE0,2,3: 16M Bytes; allows SDRAM, SBSRAM and Async   CE1: 4M Bytes; allows SBSRAM and Async only Technical Training Organization T TO

'0x Memory Scheme DevicesInternal C6201 C6204 C6205 C6701 P = 64 KB D = 64 KB C6202 P = 256 KB D = 128 KB C6203 P = 384 KB D = 512 KB   All '0x devices share same external memory map   CE0,2,3: 16M Bytes; allows SDRAM, SBSRAM and Async   CE1: 4M Bytes; allows SBSRAM and Async only   Int Prog: Cache or RAM   List of '0x devices with various internal mem sizes 0000_0000 Internal Program 0100_ _ MB External (CE0) CE0 4MB External (CE1) CE1 Internal Data 16MB External (CE0) CE2 16MB External (CE0) CE3 0200_ _ _0000 FFFF_FFFF Technical Training Organization T TO

'0x Alternate Memory Map MAP 0 FFFF_FFFF 0000_ _ M x 8 External 2 16M x 8 External _ _ M x 8 External 0 4M x 8 External 1 Internal Program 0140_0000 Internal Data 8000_0000 On-chip Peripherals 0180_ M x 8 External 0 4M x 8 External 1 Internal Program 0000_ _ _0000 MAP 1   Map 1 moves internal program to location zero   Used for boot-loading   No memory lost, only rearranged   Easy, drop-down selection between Map 0/1 with Config Tool   Map 1 moves internal program to location zero   Used for boot-loading   No memory lost, only rearranged   Easy, drop-down selection between Map 0/1 with Config Tool Technical Training Organization T TO

Outline  C6000 Memory Architecture '0x Memory Scheme  '1x Memory Scheme Technical Training Organization T TO

'1x Internal Memory 0000_0000 Level 2 Internal Memory FFFF_FFFF   Level 1 Memory   Always cache ( not in map )   L1P (prog), L1D (data)   Level 2 Memory (L2)   Program or Data   Four blocks   Each block - Cache or RAM Level 2 Prog/Data CPU Program Cache Data Cache Technical Training Organization T TO

'1x Internal Memory 0000_0000 Level 2 Internal Memory FFFF_FFFF   Level 1 Memory   Always cache ( not in map )   L1P (prog), L1D (data)   Level 2 Memory (L2)   Program or Data   Four blocks   Each block - Cache or RAM   List of '1x devices with internal mem sizes DevicesInternal C6211 C6711 C6712 C6713 L1P=4 KB L1D=4 KB L2*=64 KB C6414 C6415 C6416 L1P=16 KB L1D=16 KB L2=1 MB * C6713: L2 = 256KB Technical Training Organization T TO

'1x External Memory 0000_0000 Level 2 Internal Memory External (A2) External (A3) A000_0000 B000_0000 FFFF_FFFF External (A0) External (A1) 8000_ _0000   All external ranges   Program or Data   Sync & Async memories   Each EMIF has 4 ranges   C64x has two EMIF's External (B2) External (B3) 6800_0000 6C00_0000 External (B0) External (B1) 6000_ _0000 Level 2 Prog/Data CPU Program Cache Data Cache EMIF Technical Training Organization T TO

'1x External Memory 0000_0000 Level 2 Internal Memory External (A2) External (A3) A000_0000 B000_0000 FFFF_FFFF External (A0) External (A1) 8000_ _0000 External (B2) External (B3) 6800_0000 6C00_0000 External (B0) External (B1) 6000_ _0000 Devices EMIF (A) size of range EMIFB size of range C6211 C M Bytes (32-bits wide) N/A C671264M Bytes (16-bits wide) N/A C6414 C6415 C M Bytes (64-bits wide) 64M Bytes (16-bits wide)   All external ranges   Program or Data   Sync & Async memories   Each EMIF has 4 ranges   C64x has two EMIF's   '1x external memory details Technical Training Organization T TO

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'C6416 External Memory 0000_0000 Level 2 Internal Memory FFFF_FFFF Level 2 Prog/Data CPU Program Cache Data Cache External (CE2) External (CE3) A000_0000 B000_0000 External (CE0) External (CE1) 8000_ _0000 EMIF   Four External ranges   Program or Data   128 Mbytes each   Named: CE0, CE1, CE2, CE3   Remaining memory is unused Technical Training Organization T TO