Evolvable Hardware Questions What is it? Why do we want it? Who is it for? How do we get it?

Slides:



Advertisements
Similar presentations
Energy Efficiency, Arithmetics and Design Effort on FPGAs Case study: Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nyländen, Jani.
Advertisements

1 SECURE-PARTIAL RECONFIGURATION OF FPGAs MSc.Fisnik KRAJA Computer Engineering Department, Faculty Of Information Technology, Polytechnic University of.
Reprogrammable Hardware used in future Patient-Centric eHealth Tools Authors: Årsand E a, Hartvigsen G a, b a Norwegian Centre for Telemedicine, University.
1 Reconfigurable Hardware Thomas Polzer Overview Definition Definition Methods Methods Devices Devices Applications Applications Problems Problems.
We build generic tools for automated diagnosis & reconfiguration of distributed dynamic systems Model-Based Supervision of Composite Systems Modularity.
Tours, 20 June 2002 Field Programmable Analog Arrays: The New Art of Analog Signal Processing CRESITT Industrie Seminar Andreas Kramer.
Fault Detection in a HW/SW CoDesign Environment Prepared by A. Gaye Soykök.
Reconfigurable Computing: What, Why, and Implications for Design Automation André DeHon and John Wawrzynek June 23, 1999 BRASS Project University of California.
Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.
2/23/2009CS50901 Implementing Fault-Tolerant Services Using the State Machine Approach: A Tutorial Fred B. Schneider Presenter: Aly Farahat.
CMOL overview ● CMOS / nanowire / MOLecular hybrids ● Uses combination of Micro – Nano – Nano implements regular blocks (ie memory) – CMOS used for logic,
Evolvable Hardware: Brief introduction to the module Andy Tyrrell Department of Electronics B005 -
UCB November 8, 2001 Krishna V Palem Proceler Inc. Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc.
EMBEDDED SOFTWARE Team victorious Team Victorious.
1 A survey on Reconfigurable Computing for Signal Processing Applications Anne Pratoomtong Spring2002.
Ontogenetic systems Drawing inspiration from growth and healing processes of living organisms… …and applying them to electronic computing systems Phylogeny.
ICMetrics Experimental Platform Jenya Kovalchuk University of Essex 27 January 2012 Ecole Centrale of Lille 1 Part-financed by the European Regional Development.
Development in hardware – Why? Option: array of custom processing nodes Step 1: analyze the application and extract the component tasks Step 2: design.
1. Optimization and its necessity. Classes of optimizations problems. Evolutionary optimization. –Historical overview. –How it works?! Several Applications.
A Compact and Efficient FPGA Implementation of DES Algorithm Saqib, N.A et al. In:International Conference on Reconfigurable Computing and FPGAs, Sept.
Univ. Notre Dame, September 25, 2003 Support for Run-Time Adaptation in RAPIDware Philip K. McKinley Software Engineering and Networking Systems Laboratory.
RUNNING RECONFIGME OS OVER PETA LINUX OS MUHAMMED KHALID RAHIM DR. GRANT WIGLEY ID:
Architectures for mobile and wireless systems Ese 566 Report 1 Hui Zhang Preethi Karthik.
High Performance, Pipelined, FPGA-Based Genetic Algorithm Machine A Review Grayden Smith Ganga Floora 1.
NIMIA October 2001, Crema, Italy - Vincenzo Piuri, University of Milan, Italy NEURAL NETWORKS FOR SENSORS AND MEASUREMENT SYSTEMS Part II Vincenzo.
INTRODUCTION Crusoe processor is 128 bit microprocessor which is build for mobile computing devices where low power consumption is required. Crusoe processor.
FPGA FPGA2  A heterogeneous network of workstations (NOW)  FPGAs are expensive, available on some hosts but not others  NOW provide coarse- grained.
Reconfiguration Based Fault-Tolerant Systems Design - Survey of Approaches Jan Balach, Jan Balach, Ondřej Novák FIT, CTU in Prague MEMICS 2010.
Lecture 8: 24/5/1435 Genetic Algorithms Lecturer/ Kawther Abas 363CS – Artificial Intelligence.
1 Adrian Stoica Jet Propulsion Laboratory ehw.jpl.nasa.gov Evolvable Hardware for Automated Design and Autonomous.
HW/SW PARTITIONING OF FLOATING POINT SOFTWARE APPLICATIONS TO FIXED - POINTED COPROCESSOR CIRCUITS - Nalini Kumar Gaurav Chitroda Komal Kasat.
1 Software Design Overview Reference: Software Engineering, by Ian Sommerville, Ch. 12 & 13.
Constraint-Based Embedded Program Composition IMPACT Rapid Construction of Efficient Embedded Systems. Multiple System Variants for Little Cost. Rapid,
Page 1 Reconfigurable Communications Processor Principal Investigator: Chris Papachristou Task Number: NAG Electrical Engineering & Computer Science.
Reminder Lab 0 Xilinx ISE tutorial Research Send me an if interested Looking for those interested in RC with skills in compilers/languages/synthesis,
Embedding Constraint Satisfaction using Parallel Soft-Core Processors on FPGAs Prasad Subramanian, Brandon Eames, Department of Electrical Engineering,
Introduction to Reconfigurable Computing Greg Stitt ECE Department University of Florida.
Microelectronic Systems Institute Leandro Soares Indrusiak Manfred Glesner Ricardo Reis Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
- 1 - EE898_HW/SW Partitioning Hardware/software partitioning  Functionality to be implemented in software or in hardware? No need to consider special.
“Politehnica” University of Timisoara Course No. 2: Static and Dynamic Configurable Systems (paper by Sanchez, Sipper, Haenni, Beuchat, Stauffer, Uribe)
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
MAPLD 2005/254C. Papachristou 1 Reconfigurable and Evolvable Hardware Fabric Chris Papachristou, Frank Wolff Robert Ewing Electrical Engineering & Computer.
C OMPARING T HREE H EURISTIC S EARCH M ETHODS FOR F UNCTIONAL P ARTITIONING IN H ARDWARE -S OFTWARE C ODESIGN Theerayod Wiangtong, Peter Y. K. Cheung and.
Task Graph Scheduling for RTR Paper Review By Gregor Scott.
Rinoy Pazhekattu. Introduction  Most IPs today are designed using component-based design  Each component is its own IP that can be switched out for.
POLITECNICO DI MILANO Blanket Team Blanket Reconfigurable architecture and (IP) runtime reconfiguration support in Dynamic Reconfigurability.
R ECONFIGURABLE SECURITY SUPPORT FOR EMBEDDED SYSTEMS 1 AKSHATA VARDHARAJ.
IT-SOC 2002 © 스마트 모빌 컴퓨 팅 Lab 1 RECONFIGURABLE PLATFORM DESIGN FOR WIRELESS PROTOCOL PROCESSORS.
+ Clusters Alternative to SMP as an approach to providing high performance and high availability Particularly attractive for server applications Defined.
What is a Microprocessor ? A microprocessor consists of an ALU to perform arithmetic and logic manipulations, registers, and a control unit Its has some.
Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.
Center for Embedded Systems (CECS) Eli Bozorgzadeh Computer Science Department.
Reconfigurable architectures ESE 566. Outline Static and Dynamic Configurable Systems –Static SPYDER, RENCO –Dynamic FIREFLY, BIOWATCH PipeRench: Reconfigurable.
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
1 Advanced Digital Design Reconfigurable Logic by A. Steininger and M. Delvai Vienna University of Technology.
Evolving, Adaptable Visual Processing System Simon Fung-Kee-Fung.
Physically Aware HW/SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration Sudarshan Banarjee, Elaheh Bozorgzadeh, Nikil.
Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting.
1 Reconfigurable Environment for Analysis and Test of Software Systems Sam Martin REATSS.
A field of study that encompasses computational techniques for performing tasks that require intelligence when performed by humans. Simulation of human.
Evolvable Hardware (EHW) Topic Review S08*ENGG*6530 Antony Savich.
Control-Theoretic Approaches for Dynamic Information Assurance George Vachtsevanos Georgia Tech Working Meeting U. C. Berkeley February 5, 2003.
Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.
Reconfigurable Computing1 Reconfigurable Computing Part II.
Programmable Hardware: Hardware or Software?
Dynamo: A Runtime Codesign Environment
Introduction to Reconfigurable Computing
Anne Pratoomtong ECE734, Spring2002
Department of Electrical Engineering Joint work with Jiong Luo
Coevolutionary Automated Software Correction
Presentation transcript:

Evolvable Hardware Questions What is it? Why do we want it? Who is it for? How do we get it?

Evolution Responding to changes in environment Changes through generations The hardware's environment and changes

Hardware that changes Hardware is readjustable/reconfigurable in some way Enabling/disabling parts, reconfiguring logic Hardware is in an environment Uses idea of adaptation to change

Hardware examples Configurability necessary for adaptation Honeywell ASIC component used for evolution ”Evolvatron MK 1”

Honeywell ASIC (NASA)‏

Evolvatron MK1

The Environment Hardware - Typically in electronic device with physical constraints and factors Software - program(s) or algorithm(s) to be executed

Adaptability Dangerous places Adapt to different problems leading to simpler hardware Cost to change

Why do we want it? Research - why not? Solve new problems/solve old problems better New uses for hardware? Some uses

Evolvable vs. Not Suiting hardware to environment before or after being brought into environment Wider scope More commoditization

New Solutions Might come up with new hardware solutions Might find that one hardware solution works for many problems New hardware that does not evolve and doesn't need to incur cost of adapting

Self-Reconfigurability Less supervision Less maintainance Less tweaking

Examples Autonomous FPGA fault handling through competitive runtime reconfiguration Cell Matrix MOD 88 - self configuring platform [...]for On-chip Real-time Optimisation of Word Length and Power Consumption in a Pipelined FFT Processor targeting a MC- CDMA Receiver.

Who wants it? Extreme environments I.T./consumer Researchers

Extreme Environments Space Military Industrial Exploration

IT/consumer Servers - throughput, different problems different time of day Desktops - games, encoding Handheld - communication modes, power/heat/perormance

Research Hardware/Software designers and researchers Artificial intelligence

How do we get it? Real-time or not Software Hardware General algorithm

Real-time Circuit changes right away/on the fly Usually less supervision Difficult to control Difficult to create

Not Real-Time Circuit must break to take changes Usually more control User-defined parameter adjusting easier Easier to create

Software Genetic algorithms Genetic programming Other Metaheuristics

Hardware Anything that can be configured Dynamically configured FPGAs preferrable for many cases Sensors (heat, power, etc...)‏ Redundant parts

General Algorithm

Genetic Algorithm

Sources An Evolvable Hardware Tutorial - Jim Torresen 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005)‏