PSI - 11 Feb Status of the electronic systems of the MEG Experiment

PSI - 11 Feb Topics HV Splitter Trigger Domino Ring Sampler

PSI - 11 Feb HV  Original design works V  Microcontroller crashes if HV load changes quickly  Redesign started in Nov. ’03  Improved sensitivity 16-bit DACs, 24-bit ADCs  (linear LTC2600, analog device AD7718)  Faster microcontroller for 4 channels  (silabs C8051F310)  HV part optically decoupled from microcontroller  Communication always through the MSCB  Prototype in March ‘04

PSI - 11 Feb Splitters Milestones –End of sep 2003: 2-channels card built. –End of oct 2003: 4-channels card prototype built. –Half of nov 2003: 4 x 4-channels cards with minicrate and power supply built and tested at PSI. –End of nov 2003: test at PSI.

PSI - 11 Feb Splitter in/out 4 splitter boards with: –4 inputs 50 Ω impedance (PMT input) –4 x 2 outputs single-ended large bandwidth (DRS board and Monitor) –4 outputs differential reduced-bandwidth (Trigger) –1 adder sum of the 4 inputs (Trigger) in out diff out out adder

PSI - 11 Feb Splitter Electrical Characteristics  Based on Analog Device IC AD8009 and AD8138  Gain of x1 (modified to x10 at PSI)  Integral non-linearity <6% (5.5% typical), between 40 and 130 mV input signal;  Channel to channel crosstalk <0.2% (0.1% typical) between 40 and 200 mV input signal  Rise time <1.5ns (1.2ns typical) Gain=10

PSI - 11 Feb Timing comparison (channel F9) TDC (ns) Photoelectrons

PSI - 11 Feb Timing comparison (channel F11) TDC (ns) Photoelectrons

PSI - 11 Feb Next steps Adding single channel kill control Adding test input Increasing card density using CRG 0603 size components

PSI - 11 Feb Expected Trigger Rate Accidental background and Rejection obtained by applying cuts on the following variables photon energy photon direction hit on the positron counter time correlation positron-photon direction match The rate depends on R  R e +  R  2

PSI - 11 Feb The trigger implementation Digital approach –Flash analog-to-digital converters (FADC) –Field programmable gate array (FPGA) Final system  Only 2 different board types  Arranged in a tree structure on 3 layers  Connected with fast LVDS buses  Remote configuration/debugging capability Prototype board Check of:  the FADC-FPGA compatibility  chosen algorithms  synchronous operation  data transmission

PSI - 11 Feb Trigger prototype board : Type 0 VME 6U A-to-D Conversion Trigger I/O –16 PMT signals –2 LVDS transmitters –4 in/2 out control signals Complete system test 2 boards 16 4 Type0 Trigger Start 4 LVDS Rec Sync Trigger Start FADC FPGA Control CPLD PMT x VME Sync Clock Sync Trigger Start 4 48 LVDS Trans 3 Out Analog receivers Spare in/out Board Type0

PSI - 11 Feb The board Type0 PMT inputs LVDS transm. LVDS receiv. FADC FPGA configuration EPROMS Differential drivers package error solved with a patch board control signals.

PSI - 11 Feb Prototype system Board 0Board 1 Ancillary board Clock, sync, trigger and start distribution LVDS connection Two identical Type0 boards

PSI - 11 Feb Prototype system configuration Diff. driver Fadc Proc. Algor. LVDS Rx LVDS Tx Proc. Algor. Circ. buff Circ. buff Circ. buff Circ. buff Diff. driver Fadc Proc. Algor. LVDS Rx LVDS Tx Proc. Algor. Circ. buff Circ. buff Circ. buff Circ. buff 16 PMT input output LVDS in final Board 1 Board 0

PSI - 11 Feb Prototype system tests Debugging of the first board Type0 in Pisa –A minor error fixed System assembled at PSI in Nov. ‘03 – 100MHz synchronous operation – Negligible transmission error rate – Satisfactory operation of the analog interface Connection with the Large Prototype –PMT from #0 to #31 –Collected data Alpha Led  0

PSI - 11 Feb Alpha Time [10 ns] Amplitude [mV] Input cyclic-buffer board 1

PSI - 11 Feb LED Time [10 ns] Amplitude [mV]

PSI - 11 Feb Time [10 ns] Amplitude [mV] 00

PSI - 11 Feb Internal trigger Time [10 ns] Amplitude [mV] Max. Amplitude (  2) Index of Max Amplitude sum Pulse time Input cyclic-buffer board 0 Output cyclic-buffer board 0

PSI - 11 Feb LVDS transmission Time [10 ns] Amplitude [mV] Max. Amplitude (  2) Index of Max Amplitude sum Pulse time Output cyclic-buffer board 1 LVDS input cyclic-buffer board 0 7 clock cycles delay

PSI - 11 Feb  0 data Charge spectrum Only 32 PMT Example of data comparison

PSI - 11 Feb Further works Hardware –JTAG programming/debugging through VME by modifying the Type0 –Block transfer in A32D16 format (VME library to be modified) –Final characterization on linearity, cross talk … Analysis –Alpha, Led and  0 data to extensively check the algorithms Conclusions The prototype system met all requirements It is available to trigger the LP in future beam tests

PSI - 11 Feb Final system Trigger location: platform –Spy buffers to check the data flow are implemented –JTAG programming/debugging through VME: test planned with Type0 Final boards –VirtexII or Spartan3 ? Main FPGA XCV812E-8-FG900 is old, first production in 2000 –Connectors Analog input by 3M coaxial connectors LVDS connection by 3M cables –Differential driver on the trigger board Type1 –Other components are fixed: FADC, LVDS Tx and Rx, Clock distributor –Ancillary boards: distribution of control signals Design of final prototypes (Type1 and Type2) june 2004 –If tests are ok  start of the mass production –Estimated production and test 1 year

PSI - 11 Feb Full System Test Milestone AssemblyDesignManufactoring Prototype Board Final Prototype Jan 2002 Trigger now

PSI - 11 Feb DRS2 Chip DRS2 chip designed –500 MHz – 5 GHz sampling speed –8+2 channels, 1024 bins deep each – Readout speed up to 100 MHz (?) Production –Submitted to UMC in Nov. 18 th – 58 chips received in Jan. 15 th – packaging 3 weeks Tests planned Feb. ‘04 – April ‘04 –Redesign only if problems (next submission April or June ‘04) –Board integration – July ’04 (PSI GVME board) –Full chip production run in fall ‘04

PSI - 11 Feb DRS2 Chip Layout Domino Circuit 10 channels x 1024 bins Readout shift register 2 Test channels Die: 5 x 5 mm ~250,000 Transistors Chip: PLCC 68 Die: 5 x 5 mm ~250,000 Transistors Chip: PLCC 68

PSI - 11 Feb PSI - Generic VME PMC carrier board

PSI - 11 Feb PMC carrier board Joint effort with the MAGIC experiment (Uni. of Siena and INFN Pisa) – Clock control (locking to external source) – DRS readout with FADC – DRS control signals DRS 1 st Prototype

PSI - 11 Feb DRS (DAQ) Test Milestone AssemblyDesignManufactoring 2 nd Prototype Tests1 st Prototype Boards & ChipTest now